公开(公告)号：US20100067168A1

公开(公告)日：2010-03-18

申请号：US12514822

申请日：2007-12-11

Applicant: John D. Summers ,  Tsutomu Mutoh

Inventor： John D. Summers ,  Tsutomu Mutoh

IPC: H01G4/224

CPC classification number: H05K1/162 ,  H01G4/224 ,  H01L23/50 ,  H01L2924/0002 ,  H05K3/1291 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126 ,  H01L2924/00

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns a fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

Abstract translation: 本发明涉及组合物，以及这些组合物用于保护涂层，特别是电子器件的用途。 本发明涉及一种涂覆有复合密封剂并嵌入印刷线路板的烧制箔陶瓷电容器。

公开(公告)号：US07670919B2

公开(公告)日：2010-03-02

申请号：US11323312

申请日：2005-12-30

Applicant: John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

Inventor： John J. Tang ,  Xiang Yin Zeng ,  Jiangqi He ,  Ding Hai

IPC: H01L21/20

CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/113 ,  H05K1/162 ,  H05K3/28 ,  H05K2201/0187 ,  H05K2201/09436 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Abstract translation: 一种物品包括埋在焊接掩模中的顶部电极。 一种物品包括在核心结构上的顶部电极。 形成顶部电极的工艺包括减小焊接掩模厚度并在厚度较薄的焊接掩模上形成顶部电极。 形成顶部电极的工艺包括在位于芯结构的图案化部分中的高K电介质上形成顶部电极。

公开(公告)号：US20100035375A1

公开(公告)日：2010-02-11

申请号：US11478294

申请日：2006-06-29

Applicant: Constantine P. Grigoropoulos ,  Seung-Hwan Ko ,  Jaewon Chung ,  Dimos Poulikakos ,  Heng Pan

Inventor： Constantine P. Grigoropoulos ,  Seung-Hwan Ko ,  Jaewon Chung ,  Dimos Poulikakos ,  Heng Pan

IPC: H01L51/40 ,  B05D5/12 ,  B05D3/06 ,  H01L51/10 ,  B05C11/00 ,  H01L29/15 ,  H01G4/00 ,  H05K1/18

CPC classification number: H01L21/44 ,  H01L21/288 ,  H01L21/4867 ,  H01L21/76838 ,  H05K1/0393 ,  H05K1/162 ,  H05K3/0026 ,  H05K3/027 ,  H05K3/1241 ,  H05K3/4685 ,  H05K2201/09763 ,  H05K2203/107 ,  H05K2203/1131 ,  Y10S438/94

Abstract: The present invention relates to systems, materials and methods for the formation of conducting, semiconducting, and dielectric layers, structures and devices from suspensions of nanoparticles. Drop-on-demand systems are used in some embodiments to fabricate various electronic structures including conductors, capacitors, FETs. Selective laser ablation is used in some embodiments to pattern more precisely the circuit elements and to form small channel devices.

Abstract translation: 本发明涉及从纳米颗粒的悬浮液形成导电，半导电和电介质层，结构和器件的系统，材料和方法。 在一些实施例中使用点播系统来制造包括导体，电容器，FET的各种电子结构。 在一些实施例中使用选择性激光烧蚀来更精确地模拟电路元件并形成小通道器件。

公开(公告)号：US07589394B2

公开(公告)日：2009-09-15

申请号：US11969606

申请日：2008-01-04

Applicant: Shuichi Kawano

Inventor： Shuichi Kawano

IPC: H01L29/00 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L27/08 ,  H05K1/18

CPC classification number: H05K1/162 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/3436 ,  H05K3/423 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/0733 ,  H01L2924/00

Abstract: An interposer is constructed with a substrate body having first and second through-holes, a capacitor formed by a laminating dielectric layer and a second electrode portion on a first electrode portion, which is structured on inner surfaces of first and second through-holes and on the first surface of the substrate body. An insulation layer is formed by filling insulation material in the space within the first through-hole surrounded by second electrode portion, and a first post passes through the insulation layer, one end being electrically connected to the first electrode portion, while the first post is electrically insulated from the second electrode portion. Furthermore, a second post is formed in the second through-hole, and is connected to the second electrode portion at its peripheral surface while being electrically insulated from the first electrode portion.

Abstract translation: 内插件由具有第一通孔和第二通孔的基板本体构成，电容器由第一电极部分上的叠层电介质层和第二电极部分构成，该第一电极部分构造在第一通孔和第二通孔的内表面上， 衬底主体的第一表面。 通过在由第二电极部包围的第一通孔内的空间内填充绝缘材料形成绝缘层，第一柱通过绝缘层，一端电连接到第一电极部分，而第一柱为 与第二电极部分电绝缘。 此外，第二通孔形成在第二通孔中，并且在与第一电极部分电绝缘的同时在其外周面与第二电极部分连接。

公开(公告)号：US20090200073A1

公开(公告)日：2009-08-13

申请号：US12203340

申请日：2008-09-03

Applicant: Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

Inventor： Yasuhiko Mano ,  Atsunari Yamashita ,  Yoshitake Tsuchiya ,  Takashi Kariya

IPC: H05K1/16 ,  G03F7/20 ,  H05K3/30

CPC classification number: H05K1/162 ,  H05K3/0044 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09845 ,  H05K2203/025 ,  H05K2203/1476

Abstract: A printed wiring board includes a capacitor including a dielectric body having a first surface and a second surface, a first electrode provided on the first surface of the dielectric body, and a second electrode provided on the second surface of the dielectric body. The first electrode has an area facing and being smaller than the first surface of the dielectric body, and the second electrode has an area facing and being larger than the second surface of the dielectric body.

Abstract translation: 印刷布线板包括电容器，其包括具有第一表面和第二表面的电介质体，设置在电介质体的第一表面上的第一电极和设置在电介质体的第二表面上的第二电极。 第一电极具有面向并小于电介质体的第一表面的面积，并且第二电极具有面向并大于电介质体的第二表面的面积。

公开(公告)号：US20090140400A1

公开(公告)日：2009-06-04

申请号：US11949329

申请日：2007-12-03

Applicant: Daniel Irwin Amey, JR. ,  William Borland

Inventor： Daniel Irwin Amey, JR. ,  William Borland

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H05K1/162 ,  H01L2224/16225 ,  H05K1/112 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/09763 ,  H05K2201/10674

Abstract: A printed wiring board semiconductor package or PWB power core comprising singulated capacitors embedded on multiple layers of the printed wiring board semiconductor package wherein at least a part of each embedded capacitor lies within the die shadow and wherein the embedded, singulated capacitors comprise at least a first electrode and a second electrode. The first electrodes and second electrodes of the embedded singulated capacitors are interconnected to the Vcc (power) terminals and the Vss (ground) terminals respectively of a semiconductor device. The size of the embedded capacitors are varied to produce different self-resonant frequencies and their vertical placements within the PWB semiconductor package are used to control the inherent inductance of the capacitor-semiconductor electrical interconnections so that customized resonant frequencies of the embedded capacitors can be achieved with low impedance.

Abstract translation: 一种印刷线路板半导体封装或PWB功率核，其包括嵌入在所述印刷线路板半导体封装的多层上的单片电容器，其中每个嵌入式电容器的至少一部分位于所述管芯阴影内，并且其中所述嵌入式单片电容器包括至少第一 电极和第二电极。 嵌入式单片电容器的第一电极和第二电极分别与半导体器件的Vcc（功率）端子和Vss（接地）端子互连。 嵌入式电容器的尺寸变化以产生不同的自谐振频率，并且它们在PWB半导体封装内的垂直布置用于控制电容器 - 半导体电互连的固有电感，从而可以实现嵌入式电容器的定制谐振频率 具有低阻抗。

公开(公告)号：US20090057827A1

公开(公告)日：2009-03-05

申请号：US12129889

申请日：2008-05-30

Applicant: Takeshi SHIOGA ,  Masataka MIZUKOSHI ,  Kazuaki KURIHARA

Inventor： Takeshi SHIOGA ,  Masataka MIZUKOSHI ,  Kazuaki KURIHARA

IPC: H01G4/228 ,  H01L21/20 ,  H01L29/00

CPC classification number: H05K1/162 ,  H01G9/025 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0315 ,  Y10S438/957 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

Abstract translation: 对于用于半导体集成电路元件的电极焊盘，用于信号传输的一些电极焊盘耦合到Ti膜。 用于信号传输的其他电极焊盘通过布线在多层布线中的布线耦合到电极焊盘。 用于电源的电极焊盘耦合到电极焊盘，电极彼此不同的电力线通过布线耦合到电极焊盘。 电极焊盘也耦合到铝箔（阳极）。 用于接地的电极焊盘耦合到接地线通过布线耦合到的电极焊盘。 电极焊盘也耦合到导电聚合物膜（阴极）。

公开(公告)号：US20080291649A1

公开(公告)日：2008-11-27

申请号：US11882645

申请日：2007-08-03

Applicant: Naohiro Mashino

Inventor： Naohiro Mashino

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H01L23/50 ,  H01G4/236 ,  H01G4/33 ,  H01G4/38 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/642 ,  H01L2221/68345 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/162 ,  H05K3/007 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2203/0152 ,  H05K2203/0733 ,  Y10T29/435

Abstract: A capacitor built-in substrate of the present invention includes; a base resin layer; a plurality of capacitors arranged side by side in a lateral direction in a state that the capacitors are passed through the base resin layer, each of the capacitors constructed by a first electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively such that the projection portion on one surface side of the base resin layer serves as a connection portion, a dielectric layer for covering the projection portion of the first electrode on other surface side of the base resin layer, and a second electrode for covering the dielectric layer; a through electrode provided to pass through the base resin layer and having projection portions projected from both surface sides of the base resin layer respectively; and a built-up wiring formed on the other surface side of the base resin layer and connected to the second electrodes of the capacitors and one end side of the through electrode.

Abstract translation: 本发明的电容器内置基板包括： 基础树脂层; 在电容器通过基底树脂层的状态下，沿横向方向并排布置的多个电容器，每个电容器由设置成穿过基础树脂层并具有从两个突出部分突出的突出部分的第一电极构成 基底树脂层的表面侧分别使得基底树脂层的一个表面侧上的突出部分用作连接部分，用于覆盖基础树脂层的另一表面侧上的第一电极的突出部分的电介质层， 和用于覆盖电介质层的第二电极; 通孔，其设置成穿过所述基底树脂层，并且具有分别从所述基底树脂层的两个表面侧突出的突出部分; 以及形成在基础树脂层的另一表面侧并与电容器的第二电极和贯通电极的一端侧连接的积层布线。

公开(公告)号：US20080266031A1

公开(公告)日：2008-10-30

申请号：US12060941

申请日：2008-04-02

Applicant: Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

Inventor： Yutaka UEMATSU ,  Hideki Osaka ,  Yoji Nishio ,  Eiichi Suzuki

IPC: H01P1/00

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/111 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10515 ,  H05K2201/10522 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.

Abstract translation: 提供了能够实现半导体器件的安装密度和噪声降低的改进的技术。 安装在印刷电路板上的LSI包括接地BGA球和电源BGA球，以从印刷线路板获得电源，并且接地BGA球和电源BGA球彼此靠近地布置。 去耦电容器安装在印刷电路板上，并具有第一端子和第二端子。 接地BGA球和第一端子通过第一金属电极板连接，电力BGA球和第二端子通过第二金属电极板连接。 第一金属电极板和第二金属电极板在其间插入厚度等于或小于1μm的电介质膜。

公开(公告)号：US07436678B2

公开(公告)日：2008-10-14

申请号：US10967569

申请日：2004-10-18

Applicant: David Ross McGregor

Inventor： David Ross McGregor

IPC: H05K7/00

CPC classification number: H05K1/167 ,  H01L2924/19105 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/1453 ,  Y10T29/49101 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

Abstract: A capacitive/resistive device provides both resistive and capacitive functions. The capacitive/resistive device may be embedded within a layer of a printed wiring board. Embedding the capacitive/resistive device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability.

Abstract translation: 电容/电阻器件提供电阻和电容功能。 电容/电阻装置可以嵌入印刷电路板的层内。 嵌入电容/电阻器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。