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公开(公告)号:US09660616B2
公开(公告)日:2017-05-23
申请号:US14865905
申请日:2015-09-25
CPC分类号: H03K3/012 , G06F1/3203 , G06F1/324 , G06F1/3296 , H01L2924/00 , H01L2924/0002 , H02J4/00 , Y02D10/126 , Y02D10/172 , Y02D50/20 , Y10T307/406 , Y10T307/414
摘要: Systems and methods for managing power in an integrated circuit using power islands are disclosed. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.
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公开(公告)号:US20170139468A1
公开(公告)日:2017-05-18
申请号:US15394565
申请日:2016-12-29
申请人: APPLE INC.
发明人: Daniel Wilson , Anand Dalal , Josh De Cesare
IPC分类号: G06F1/32 , G06F13/364 , G06F13/42
CPC分类号: G06F15/17362 , G06F1/3287 , G06F13/364 , G06F13/4282 , G06F13/4295 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要: Methods and apparatus for managing connections be multiple internal integrated circuits (ICs) of for example, a high-speed internal device interface. Improved schemes for coordination of connection and disconnection events, and/or suspension and resumption of operation for a High-Speed Inter. Chip™ (HSIC) in are disclosed. In one exemplary embodiment, a “device”-initiated and “host”-initiated connect/disconnect procedure is disclosed, that provides improved dining, synchronization, and power consumption.
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公开(公告)号:US20170139467A1
公开(公告)日:2017-05-18
申请号:US15346865
申请日:2016-11-09
CPC分类号: G06F1/3287 , G06F1/266 , G06F13/385 , G06F13/4022 , G06F13/4282 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要: Described examples include USB port controllers with a control circuit configured to switch from a normal first power mode to a second power mode for reduced power consumption in response a command from a port manager circuit, and to switch from the second power mode to the first power mode in response to detected activity on a communications connection, or a detected connection of a USB device to a USB port connector. After switching back to the first power mode in response to detected communications activity, the control circuit automatically switches operation of the USB port controller back to the second power mode unless a communications transaction addressed to the USB port controller is received within a non-zero certain time after switching from the second power mode to the first power mode.
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公开(公告)号:US09641713B2
公开(公告)日:2017-05-02
申请号:US13594995
申请日:2012-08-27
CPC分类号: H04N1/00891 , H04L12/12 , H04N1/00896 , H04N1/00907 , H04N1/32502 , H04N2201/0094 , Y02D50/20 , Y02D50/40
摘要: A power-saving mode deactivation apparatus for performing communication via a communication network with specific processing apparatuses for particular processing is provided. The power-saving mode deactivation apparatus includes a storage portion for storing therein a deactivation method for deactivating a power-saving mode of each of the specific processing apparatuses; a detection portion for detecting that particular processing data for the particular processing is not delivered to, among the specific processing apparatuses, a destination specific processing apparatus of the particular processing data, and a deactivation portion for performing, when the detection portion detects that the particular processing data is not delivered to the destination specific processing apparatus, deactivation processing for deactivating a power-saving mode of the destination specific processing apparatus based on the deactivation method, stored in the storage portion, for the destination specific processing apparatus.
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公开(公告)号:US09626126B2
公开(公告)日:2017-04-18
申请号:US13869622
申请日:2013-04-24
发明人: Mehmet Iyigun , Yevgeniy M. Bak , Eric M. Bluestein , Robin A. Alexander , Andrew M. Herron , Xiaozhong Xing
CPC分类号: G06F3/068 , G06F1/3268 , G06F3/0625 , G06F3/0647 , G06F3/0653 , G06F3/0685 , G06F12/14 , Y02D10/154 , Y02D50/20
摘要: A hybrid drive includes multiple parts: a performance part (e.g., a flash memory device) and a base part (e.g., a magnetic or other rotational disk drive). A drive access system, which is typically part of an operating system of a computing device, issues input/output (I/O) commands to the hybrid drive to store data to and retrieve data from the hybrid drive. The drive access system supports multiple priority levels and obtains priority levels for groups of data identified by logical block addresses (LBAs). The LBAs read while the device is operating in a power saving mode are assigned a priority level that is at least the lowest of the multiple priority levels supported by the device, increasing the likelihood that LBAs read while the device is operating in the power saving mode are stored in the performance part of the hybrid drive.
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公开(公告)号:US09625980B2
公开(公告)日:2017-04-18
申请号:US14571667
申请日:2014-12-16
发明人: Rob E. Cosaro
CPC分类号: G06F1/3287 , G06F1/3237 , G06F1/324 , G06F1/325 , G06F1/3253 , G06F1/3296 , G06F9/4418 , G06F13/24 , Y02D10/126 , Y02D10/128 , Y02D10/151 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要: The present disclosure provides for a method and semiconductor device for low power configuration. In one embodiment, a method includes receiving a packet from a host device, where the packet is received at a USB (Universal Serial Bus) device. The method also includes detecting, by the USB device, that the packet includes an endpoint address of a low power endpoint. The method also includes entering a low power mode state, in response to the detecting, where the USB device includes a USB clock domain that includes an internal reference clock (IRC) and clock recovery logic, and a clock tree block located outside of the USB clock domain. The entering the low power mode state includes disabling the clock tree block, and clocking the USB clock domain using the IRC and clock recovery logic.
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87.
公开(公告)号:US09619377B2
公开(公告)日:2017-04-11
申请号:US14458949
申请日:2014-08-13
申请人: Apple Inc.
发明人: Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC分类号: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号:US09619015B2
公开(公告)日:2017-04-11
申请号:US14375831
申请日:2012-07-27
申请人: Louis B. Hobson
发明人: Louis B. Hobson
CPC分类号: G06F1/3296 , G06F1/3203 , G06F1/3234 , G06F1/3275 , G06F9/4418 , G06F9/442 , Y02D50/20
摘要: Example embodiments disclosed herein relate to implementing a power down state in a computing device. A sleep command is issued to place a computing device in a sleep state in response to receipt of a power off command at the computing device. Content of memory of the computing device is written to non-volatile storage of the computing device and the computing device is placed in a power off state.
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公开(公告)号:US09619009B2
公开(公告)日:2017-04-11
申请号:US12980532
申请日:2010-12-29
申请人: Efraim Rotem , Oren Lamdan , Alon Naveh
发明人: Efraim Rotem , Oren Lamdan , Alon Naveh
IPC分类号: G06F1/00 , G06F1/32 , G06F1/20 , G06F9/38 , G06F12/0862 , G06F12/0875
CPC分类号: G06F1/3287 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/324 , G06F1/3243 , G06F1/3275 , G06F1/3296 , G06F9/30083 , G06F9/3814 , G06F12/0862 , G06F12/0875 , G06F2212/452 , G06F2212/602 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D50/20
摘要: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at a performance level different than a performance level at which another one of the plurality of processor cores may operate. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. Other embodiments are also disclosed.
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90.
公开(公告)号:US20170097673A1
公开(公告)日:2017-04-06
申请号:US14872666
申请日:2015-10-01
发明人: Delali Dogbey , Randhir S. Malik , Brian C. Totten
IPC分类号: G06F1/32
CPC分类号: G06F1/3296 , G06F1/26 , G06F1/3206 , G06F1/3287 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要: A computer system includes power-consuming components, a power supply providing power to the power-consuming components, a single power bus extending from the power supply to each of the system components, and a service processor in communication with the components and the power supply. The service processor sends a turn on signal to the power supply in response to detecting activity of the power-consuming components and sends a sleep mode signal to the power supply in response to detecting inactivity of the power-consuming components. The power supply supplies power to the single power bus at a first voltage in response to receiving the turn on signal and supplies power to the single power bus at a second voltage in response to receiving the sleep mode signal, wherein the first voltage is greater than the second voltage.
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