摘要:
A method of fabricating an interconnect element may include fabricating a metal layer that overlies a carrier layer and that includes a plurality of metal traces; providing a dielectric element to overlie the metal layer and the carrier layer; providing a plurality of metal posts; and removing the carrier layer to expose the first major surface of the dielectric element and the outer surfaces of the plurality of metal traces.
摘要:
A method for forming a bump structure and a bump structure for conductive interconnection with another element having at least one of microelectronic devices or wiring thereon, used as an electric connection in an electronic circuit, includes the steps of forming a mandrel by steps including forming at least one opening extending through a bump-forming die body in the thickness direction thereof and positioning a bump-forming die lid on a surface of the bump-forming die body so as to cover one end of the opening and to thereby define a bump-forming recess. The bump-forming die body may be comprised of a metal sheet. A metal layer is formed at least on an inner surface of the bump-forming die lid exposed within the bump-forming recess. The mandrel is removed so as to expose the metal layer and form a bump structure.
摘要:
An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.
摘要:
An interconnect element is provided which includes a dielectric element having a first major surface, a second major surface remote from the first major surface, and a plurality of recesses extending inwardly from the first major surface. A plurality of metal traces are embedded in the plurality of recesses, the metal traces having outer surfaces substantially co-planar with the first major surface and inner surfaces remote from the outer surfaces. A plurality of posts extend from the inner surfaces of the plurality of metal traces through the dielectric element, the plurality of posts having tops exposed at the second major surface. A multilayer wiring board including a plurality of such interconnect elements is also provided, as well as various methods for making such interconnect elements and multilayer wiring boards.
摘要:
A method of making a microelectronic assembly includes providing a conductive metal layer having a first surface and a second surface, and etching the first surface of the conductive metal layer to form conductive protrusions, whereby after the etching step, the second surface of the conductive metal layer defines a substantially flat, continuous surface. The method includes juxtaposing a layer of an insulating material with tips of the conductive protrusions, and pressing the conductive protrusions through the layer of an insulating material so that the tips of the conductive protrusions are accessible at a first surface of the layer of an insulating material.
摘要:
To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an inter layer insulating film allows for inter layer connection between plural wiring films insulated from one another with plural inter layer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the inter layer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 μm or smaller, and the multilayer wiring board itself for the electronic device has the flexibility.
摘要:
A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are provided in which second interconnect elements which do not have co-planar interconnect patterns are integrated therewith as intermediate elements, and the resulting multilayer interconnect element has co-planar interconnect patterns.
摘要:
A process for manufacturing a multilayer wiring board including the steps of forming an insulating layer on a base provided with a bump for interlayer connection, bonding a copper foil onto the insulating layer by a thermocompression bonding by sandwiching the copper foil between stainless steel plates, and patterning the copper foil, in which a metal foil is interposed at least between each of the stainless plates and the copper foil at the time of the thermocompression bonding. At this time, a mold release layer is formed on a surface of the metal foil to be imposed. Thus, such a multilayer wiring board can be manufactured that prevents sticking of a product after molding (cementing of the copper foil) and excels in dimensional stability without occurrence of wrinkling and ruggedness.
摘要:
A connecting member between wiring films is provided in which: a normal copper foil, which is a general-purpose component and not expensive, or the like can be used as a material; formation of bumps is sufficiently achieved by conducting etching one time; and a necessary number of layers can be laminated and pressed collectively at a time. Bumps, which are formed approximately in a cone-shape, for connecting wiring films of a multilayer wiring substrate are embedded in a second resin film that serves as an interlayer insulating film.
摘要:
A method is provided for manufacturing a multi-layer wiring circuit substrate. A first metal layer is selectively etched in first areas to reduce a thickness of the metal layer in the first areas and to form protrusions in other areas which extend above the etched areas. An interlayer-insulating layer is formed to overlie the etched areas of the first metal layer. The interlayer-insulating layer has an inner surface which confronts the etched first areas and an outer surface remote from the inner surface, such that the protrusions extend through the interlayer-insulating layer and have ends exposed at the outer surface. A second metal layer is then provided in conductive communication with the exposed ends of the protrusions, and the first and second metal layers are selectively patterned from surfaces remote from the interlayer-insulating layer.