摘要:
A camera system may include an optics stack including two substrates secured together in a vertical direction and an optical system on the two substrates, the two substrates having exposed sides, a detector on a detector substrate, and a stray light blocker directly on at least some sides of the optics stack.
摘要:
Image sensors are provided having a plurality of photodetectors in a detector layer Optionally, an optically transparent substrate is provided for a rear-illuminated sensor architecture. The photodetectors may be arranged in three or more arrays. Typically, each array is contiguous and is associated with light of a different color and/or wavelength. In addition, the arrays may be coplanar, or, in the alternative, located at increasing distances from a light-receiving surface in an at least partially nonoverlapping manner. Also provided are image sensor packages.
摘要:
Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
摘要:
A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.
摘要:
A capped chip is provided which includes a chip having a front surface, a plurality of conductive features exposed at the front surface and a cap. The cap has an inner surface facing the front surface of the chip, an outer surface opposite the inner surface, and a through hole extending from the outer surface to the inner surface. A conductive interconnect extends at least partially through the through hole. The interconnect includes a conductive article which occupies a substantial portion of a volume of the interconnect and the interconnect further includes a flowable conductive medium which joins the conductive article to at least one of the plurality of conductive features of the chip or to the cap.
摘要:
A connection component including a flexible substrate having a top surface and a bottom surface, a layer of a compliant, dielectric material overlying the top surface of the substrate, the compliant material layer having a top surface remote from the substrate, an array of flexible, conductive leads having first ends attached to terminals accessible at the bottom surface of the substrate and second ends adjacent the top surface of the compliant layer, wherein each lead comprises a core of a first conductive material surrounded by a layer of a second conductive material, the second conductive material having a greater yield strength than the first conductive material.
摘要:
Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.
摘要:
Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
摘要:
A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.
摘要:
Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.