公开(公告)号：US08735258B2

公开(公告)日：2014-05-27

申请号：US13343903

申请日：2012-01-05

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

IPC分类号： H01L21/02 ,  H01L21/20

CPC分类号： H01L21/02 ,  H01L21/20 ,  H01L27/0629 ,  H01L28/20

摘要： Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

摘要翻译： 提供了制造包括金属栅极晶体管和电阻器的半导体器件的方法。 一种方法包括提供包括晶体管器件区域和隔离区域的衬底，在晶体管器件区域上形成虚拟栅极，在隔离区域上形成电阻器，以及用掺杂剂注入电阻器。 该方法还包括湿式蚀刻伪栅极以去除虚拟栅极，然后在晶体管器件区域上形成金属栅极以替代伪栅极。

公开(公告)号：US20130178039A1

公开(公告)日：2013-07-11

申请号：US13343903

申请日：2012-01-05

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Shyh-Wei Wang

IPC分类号： H01L21/02

CPC分类号： H01L21/02 ,  H01L21/20 ,  H01L27/0629 ,  H01L28/20

摘要： Methods of fabricating a semiconductor device including a metal gate transistor and a resistor are provided. A method includes providing a substrate including a transistor device region and an isolation region, forming a dummy gate over the transistor device region and a resistor over the isolation region, and implanting the resistor with a dopant. The method further includes wet etching the dummy gate to remove the dummy gate, and then forming a metal gate over the transistor device region to replace the dummy gate.

摘要翻译： 提供了制造包括金属栅极晶体管和电阻器的半导体器件的方法。 一种方法包括提供包括晶体管器件区域和隔离区域的衬底，在晶体管器件区域上形成虚拟栅极，在隔离区域上形成电阻器，以及用掺杂剂注入电阻器。 该方法还包括湿式蚀刻伪栅极以去除虚拟栅极，然后在晶体管器件区域上形成金属栅极以替代伪栅极。

公开(公告)号：US20130092985A1

公开(公告)日：2013-04-18

申请号：US13272875

申请日：2011-10-13

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/20

CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/66636

摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.

摘要翻译： 一个实施例是半导体结构。 半导体结构包括外延区域，栅极结构，接触间隔物和蚀刻停止层。 外延区域在衬底中。 外延区的顶表面从衬底的顶表面升高，并且外延区具有在衬底的顶表面和外延区的顶表面之间的刻面。 栅极结构在衬底上。 接触间隔物横向在外延区域的小面和栅极结构之间。 蚀刻停止层在每个接触间隔物和外延区域的顶表面之上并相邻。 接触间隔物的蚀刻选择性与蚀刻停止层的蚀刻选择性的比率等于或小于3:1。

公开(公告)号：US08324690B2

公开(公告)日：2012-12-04

申请号：US12861642

申请日：2010-08-23

申请人： Jyh-Huei Chen

发明人： Jyh-Huei Chen

IPC分类号： H01L29/76

CPC分类号： H01L29/7843 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/78

摘要： A composite dielectric layer including a tensile stressed nitride layer over an oxide layer serves the dual function of acting as an SMT (stress memorization technique) film while an annealing operation is carried out and then remains partially intact as it is patterned to further serve as an RPO film during a subsequent silicidation process. The composite dielectric layer covers part of a semiconductor substrate that includes a gate structure. The tensile stressed nitride layer protects the oxide layer and alleviates oxide damage during a pre-silicidation PAI (pre-amorphization implant) process. Portions of the gate structure and the semiconductor substrate not covered by the composite dielectric layer include amorphous portions that include the PAI implanted dopant impurities. A silicide material is disposed on the gate structure and portions of the semiconductor substrate not covered by the composite dielectric layer.

摘要翻译： 包括氧化物层上的拉伸应力氮化物层的复合电介质层用于作为SMT（应力记忆技术）膜的双重功能，同时执行退火操作，然后保持部分完整，因为其被图案化以进一步用作 在随后的硅化过程中的RPO膜。 复合介电层覆盖包括栅极结构的半导体衬底的一部分。 拉伸应力氮化物层保护氧化物层并减轻在预硅化PAI（非晶化前植入）过程中的氧化物损伤。 未被复合电介质层覆盖的栅极结构和半导体衬底的部分包括包含PAI注入掺杂杂质的非晶部分。 硅化物材料设置在栅极结构上，半导体衬底的未被复合电介质层覆盖的部分。

公开(公告)号：US20120289040A1

公开(公告)日：2012-11-15

申请号：US13107636

申请日：2011-05-13

申请人： Chun-Hung HUANG ,  Yu-Hsien LIN ,  Ming-Yi LIN ,  Jyh-Huei CHEN

发明人： Chun-Hung HUANG ,  Yu-Hsien LIN ,  Ming-Yi LIN ,  Jyh-Huei CHEN

IPC分类号： H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： An integrated circuit device and method for manufacturing an integrated circuit device is disclosed. The integrated circuit device comprises a core device and an input/output circuit. Each of the core device and input/output circuit includes a PMOS structure and an NMOS structure. Each of the PMOS includes a p-type metallic work function layer over a high-k dielectric layer, and each of the NMOS structure includes an n-type metallic work function layer over a high-k dielectric layer. There is an oxide layer under the high-k dielectric layer in the input/output circuit.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 集成电路装置包括核心装置和输入/输出电路。 核心器件和输入/输出电路中的每一个包括PMOS结构和NMOS结构。 每个PMOS包括在高k电介质层上的p型金属功函数层，并且每个NMOS结构包括在高k电介质层上的n型金属功函数层。 在输入/输出电路中的高k电介质层下方有氧化层。

公开(公告)号：US20120248510A1

公开(公告)日：2012-10-04

申请号：US13077257

申请日：2011-03-31

申请人： Jung-Tzu HSU ,  Ching-Chung PAI ,  Yu-Hsien LIN ,  Jyh-Huei CHEN

发明人： Jung-Tzu HSU ,  Ching-Chung PAI ,  Yu-Hsien LIN ,  Jyh-Huei CHEN

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/7848

摘要： The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

摘要翻译： 本公开提供了用于在替代栅极结构中去除虚设多晶硅层期间防止在衬底背面暴露多晶硅蚀刻化学物质的多晶硅层和硅衬底的方法和结构。 使用热沉积工艺或工艺沉积用于偏置间隔物和/或接触蚀刻停止层（CESL）的电介质层以覆盖衬底背面上的多晶硅层。 由于在后侧斜面处的多晶硅层的完全去除以及由此导致的硅衬底的蚀刻，这种机理减少或消除了源自衬底背面的斜面的颗粒。

公开(公告)号：US07678655B2

公开(公告)日：2010-03-16

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US20070232043A1

公开(公告)日：2007-10-04

申请号：US11395212

申请日：2006-04-03

申请人： Jyh-Huei Chen ,  Mei-Yun Wang ,  Tze-Liang Lee

发明人： Jyh-Huei Chen ,  Mei-Yun Wang ,  Tze-Liang Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/28097 ,  H01L21/28202 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/665 ,  H01L29/78

摘要： A method for forming a silicide layer on a substrate. A substrate with a silicon surface is provided. Nitrogen is incorporated into the silicon surface by a plasma treatment, to form a nitridized silicon surface. A metal layer is formed on the nitridized silicon surface. The substrate having the metal layer thereon is annealed to form a silicide layer between the metal layer and the substrate.

摘要翻译： 一种在衬底上形成硅化物层的方法。 提供具有硅表面的衬底。 通过等离子体处理将氮掺入硅表面，形成氮化硅表面。 在氮化硅表面上形成金属层。 对其上具有金属层的基板进行退火，以在金属层和基板之间形成硅化物层。

公开(公告)号：US06444566B1

公开(公告)日：2002-09-03

申请号：US09845481

申请日：2001-04-30

申请人： Ming Huan Tsai ,  Jyh Huei Chen ,  Chu Yun Fu ,  Hun Jan Tao

发明人： Ming Huan Tsai ,  Jyh Huei Chen ,  Chu Yun Fu ,  Hun Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834

摘要： Borderless contacts are used in integrated circuits in order to conserve chip real estate. As part of the process for manufacturing borderless contacts, an etch-stopping layer of silicon nitride is first laid over the area that is to be contacted. Investigation has now shown that this can lead to damage to the silicon at the edges of the via. The present invention eliminates this damage by introducing a buffer layer between the silicon surface and said sidon nitride layer. Suitable materials for the buffer layer that have been found to be infective include silicon oxide and silicon oxynitride with the latter offering some ditional advantages over the former. Experimental data confirming the effectiveness of the buffer layer are provided, together with a process for its manufacture.

摘要翻译： 无边界接触用于集成电路，以节省芯片的不动产。 作为制造无边界接触的工艺的一部分，首先将氮化硅的蚀刻停止层铺设在要接触的区域上。 现在调查显示，这可能导致在通孔边缘的硅损坏。 本发明通过在硅表面和所述侧氮化物层之间引入缓冲层来消除这种损害。 已经发现感染的缓冲层的合适材料包括氧化硅和氮氧化硅，后者提供了比前者更多的优点。 提供确认缓冲层有效性的实验数据及其制造方法。

公开(公告)号：US08877614B2

公开(公告)日：2014-11-04

申请号：US13272875

申请日：2011-10-13

申请人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

发明人： Chun-Hung Ko ,  Jyh-Huei Chen ,  Ming-Jie Huang

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/20 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L21/76834 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/66636

摘要： An embodiment is a semiconductor structure. The semiconductor structure comprises an epitaxial region, a gate structure, a contact spacer, and an etch stop layer. The epitaxial region is in a substrate. A top surface of the epitaxial region is elevated from a top surface of the substrate, and the epitaxial region has a facet between the top surface of the substrate and the top surface of the epitaxial region. The gate structure is on the substrate. The contact spacer is laterally between the facet of the epitaxial region and the gate structure. The etch stop layer is over and adjoins each of the contact spacer and the top surface of the epitaxial region. A ratio of an etch selectivity of the contact spacer to an etch selectivity of the etch stop layer is equal to or less than 3:1.

摘要翻译： 一个实施例是半导体结构。 半导体结构包括外延区域，栅极结构，接触间隔物和蚀刻停止层。 外延区域在衬底中。 外延区的顶表面从衬底的顶表面升高，并且外延区具有在衬底的顶表面和外延区的顶表面之间的刻面。 栅极结构在衬底上。 接触间隔物横向在外延区域的小面和栅极结构之间。 蚀刻停止层在每个接触间隔物和外延区域的顶表面之上并相邻。 接触间隔物的蚀刻选择性与蚀刻停止层的蚀刻选择性的比率等于或小于3:1。