公开(公告)号：US08115310B2

公开(公告)日：2012-02-14

申请号：US12482855

申请日：2009-06-11

申请人： Kenji Masumoto ,  Mutsumi Masumoto

发明人： Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L23/48

CPC分类号： H01L23/49811 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/13016 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16057 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

摘要翻译： 半导体器件组件可以包括半导体芯片，接收衬底和插入在半导体芯片和接收衬底之间的间隔结构。 间隔件在柱和粘结指之间提供了一个空余的空余物，用于过剩的导电材料，否则可能会从柱和键指之间流出，导致导电短路。 间隔件还可以提供柱和粘合指之间的偏移。

公开(公告)号：US20100255641A1

公开(公告)日：2010-10-07

申请号：US12756053

申请日：2010-04-07

申请人： Noboru NAKANISHI ,  Kazunori HAYATA ,  Mutsumi MASUMOTO

发明人： Noboru NAKANISHI ,  Kazunori HAYATA ,  Mutsumi MASUMOTO

IPC分类号： H01L21/56

CPC分类号： H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/75611 ,  H01L2224/7565 ,  H01L2224/81092 ,  H01L2224/81097 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81205 ,  H01L2224/814 ,  H01L2224/8309 ,  H01L2224/83097 ,  H01L2224/83104 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05552 ,  H01L2924/00012

摘要： The objective of this invention is to present a semiconductor device manufacturing method with which the formation of voids inside an underfill resin can be prevented using a simple configuration. The semiconductor device manufacturing method of the present invention involves a step in which multiple electrodes formed on one principal surface of each semiconductor chip 20 are flip-chip bonded to corresponding conductive areas formed on a substrate, a step (condition 1) in which liquid underfill resin 40 is supplied along the circumferences of semiconductor chips 20 mounted on the substrate in the atmospheric pressure so as to form air pocket 110 between each semiconductor chip 20 and substrate 30, a step (conditions 2, 3, 4) in which the substrate is transferred from the atmospheric pressure into a vacuum atmosphere in order to discharge the air from air pockets 110, and a step (conditions 5, 6, 7, 8) in which the substrate is transferred from the vacuum atmosphere into the atmospheric pressure in order to let underfill resin 40 advance deep in the semiconductor chips.

摘要翻译： 本发明的目的是提供一种半导体器件制造方法，利用该半导体器件制造方法，可以使用简单的构造来防止底部填充树脂内的空隙的形成。 本发明的半导体器件制造方法涉及将形成在各半导体芯片20的一个主面上的多个电极倒装贴合在形成于基板上的相应的导电区域的步骤，其中液体底部填充的步骤（条件1） 树脂40沿着大气压下安装在基板上的半导体芯片20的周边供给，以便在每个半导体芯片20和基板30之间形成气袋110，其中基板为 从空气压力转移到真空气氛中以从气穴110排出空气，以及将基板从真空气氛转移到大气压中的步骤（条件5,6,7,8），以便 让底部填充树脂40在半导体芯片中深入。

公开(公告)号：US20100237511A1

公开(公告)日：2010-09-23

申请号：US12793537

申请日：2010-06-03

申请人： Mutsumi MASUMOTO

发明人： Mutsumi MASUMOTO

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has one or more semiconductor chips with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments separated from the chip by gaps; the segments have first and second surfaces, wherein the second surfaces are coplanar with the passive chip surface. Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 μm. Reflow metals may be on the passive chip surface and the second segment surfaces.

摘要翻译： 半导体器件具有一个或多个具有有源和无源表面的半导体芯片，其中有源表面包括接触焊盘。 该装置还具有通过间隙与芯片分离的多个金属段; 所述段具有第一和第二表面，其中所述第二表面与所述无源芯片表面共面。 导电连接器跨越从芯片接触焊盘到相应的第一段表面。 聚合物封装化合物覆盖有源芯片表面，连接器和第一分段表面，并且填充间隙使得化合物形成与被动芯片表面和第二分段表面共面的表面。 在该结构中，器件厚度可以仅为约250μm。 回流金属可能在无源芯片表面和第二段表面上。

公开(公告)号：US20090011538A1

公开(公告)日：2009-01-08

申请号：US11887212

申请日：2006-03-13

申请人： Mutsumi Masumoto ,  Katsumi Terada

发明人： Mutsumi Masumoto ,  Katsumi Terada

IPC分类号： H01L21/00

CPC分类号： H01L21/67109 ,  H01L21/563 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/75 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/14 ,  H01L2924/15788 ,  Y10T29/41 ,  H01L2924/00

摘要： A mounting system is provided with a substrate loader section, a chip mounting section, and a substrate unloader section for sequentially taking out substrates whereupon chips are mounted. The mounting system is characterized in that the substrate loader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates, a stage heater for heating/heat insulating a substrate is provided, respectively, at a substrate conveying portion from a substrate waiting stage for the chip mounting section to the chip mounting section, at the chip mounting section, and at a substrate conveying portion from the chip mounting section to the substrate unloader section, and the substrate unloader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates whereupon chips are mounted. The substrate can be sustained at a desirable temperature over the substantially entire mounting process having a series of steps, and in particular, occurrence of problems ascribed to moisture absorption can be suppressed or prevented.

摘要翻译： 安装系统设置有基板装载部分，芯片安装部分和基板卸载部分，用于顺序取出安装芯片的基板。 安装系统的特征在于，基板装载部分设置有能够将基板与能够容纳多个基板的基板隔套一起隔热的烘箱，分别设置用于加热/隔热基板的台加热器， 在从芯片安装部的基板等待台到芯片安装部，芯片安装部以及从芯片安装部到基板卸载部的基板输送部的基板输送部，基板卸载部是 提供了能够将基板与能够容纳多个基板并因此安装芯片的基板隔套一起烘烤的炉。 可以在具有一系列步骤的基本上整个安装过程中将基材维持在期望的温度，并且特别地，可以抑制或防止归因于吸湿的问题的发生。

公开(公告)号：US07459339B2

公开(公告)日：2008-12-02

申请号：US11538626

申请日：2006-10-04

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The objective of the invention is to provide a semiconductor device manufacturing method that can suppress the formation of voids in the underfill resin and realize a highly reliable flip-chip assembly. The semiconductor device manufacturing method pertaining to the present invention comprises the following processing steps: a step of operation in which a plurality of electrodes 24, formed in a two-dimensional array on a principal surface 22 of semiconductor chip 20, are connected to corresponding conductive regions 32, 34 on substrate 30, a step of operation in which underfill resin 40 is supplied between the principal surface of the semiconductor chip and the substrate, and a step of operation in which the semiconductor chip and substrate with supplied underfill resin 40 are exposed to atmospheric pressure.

摘要翻译： 本发明的目的是提供一种半导体器件制造方法，其可以抑制底部填充树脂中的空隙的形成，并实现高可靠性的倒装芯片组装。 本发明的半导体器件制造方法包括以下处理步骤：将半导体芯片20的主表面22上形成为二维阵列的多个电极24连接到相应的导电性的工序 在基板30上的区域32,34，在半导体芯片的主表面和基板之间供给底部填充树脂40的操作步骤以及具有供给的底部填充树脂40的半导体芯片和基板暴露的操作步骤 到大气压力。

公开(公告)号：US20070132075A1

公开(公告)日：2007-06-14

申请号：US11299594

申请日：2005-12-12

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second surfaces (111b) are coplanar (130) with the passive chip surface (101b). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound (150) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar (130) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 μm. Reflow metals may be on the passive chip surface and the second segment surfaces.

摘要翻译： 半导体器件（100）具有一个或多个具有有源和无源表面的半导体芯片（110），其中所述有源表面包括接触焊盘。 该装置还具有通过间隙（120）从芯片分离的多个金属段（111）。 所述段具有第一和第二表面，其中所述第二表面（111b）与所述无源芯片表面（101b）共面（130）。 导电连接器跨越从芯片接触焊盘到相应的第一段表面。 聚合物封装化合物（150）覆盖有源芯片表面，连接器和第一分段表面，并且填充间隙使得化合物与无源芯片表面和第二分段表面共面（130）形成表面。 在该结构中，器件厚度可以仅为约250μm。 回流金属可能在无源芯片表面和第二段表面上。

公开(公告)号：US07157363B2

公开(公告)日：2007-01-02

申请号：US10949386

申请日：2004-09-27

申请人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

发明人： Takanao Suzuki ,  Masatoshi Inaba ,  Tadanori Ominato ,  Masahiro Kaizu ,  Akihito Kurosaka ,  Masatoshi Inaba ,  Nobuyuki Sadakata ,  Mutsumi Masumoto ,  Kenji Masumoto

IPC分类号： H01L21/44

CPC分类号： H01L24/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014

摘要： An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

摘要翻译： 形成在与电极焊盘（2）相适应的位置处具有开口部（3a）的绝缘层（3）。 接着，在绝缘层（3）上形成树脂突起部（4）。 此后，形成抗蚀剂膜，该抗蚀剂膜具有在与开口部分（31a）相适应的区域中形成的开口部分，树脂突出部分（4）和夹在其间的区域。 通过使用抗蚀剂膜作为掩模，通过电解铜电镀形成Cu镀层（6）。

公开(公告)号：US06734532B2

公开(公告)日：2004-05-11

申请号：US10006576

申请日：2001-12-06

申请人： Sreenivasan K. Koduri ,  Kenji Masumoto ,  Mutsumi Masumoto

发明人： Sreenivasan K. Koduri ,  Kenji Masumoto ,  Mutsumi Masumoto

IPC分类号： H01L2358

CPC分类号： H01L23/562 ,  H01L23/3157 ,  H01L23/552 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01087 ,  H01L2924/04941

摘要： A semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit and input/output pads suitable for metallurgical contacts. Further, the device has a protective plastic film (polyimide, epoxy resin, or silicone) of controlled and uniform thickness (20 to 60 &mgr;m) selectively attached to the passive surface. The film is suitable to absorb light of visible and ultraviolet wavelengths, to remain insensitive to moisture absorption, and to exert thermomechanical stress on the chip such that this stress at least partially neutralizes the stress exerted by an outside part after chip assembly.

摘要翻译： 一种半导体器件，包括具有有源和无源表面的半导体芯片; 主动表面包括集成电路和适用于冶金接触的输入/输出焊盘。 此外，该装置具有选择性地连接到被动表面的受控均匀厚度（20至60μm）的保护性塑料膜（聚酰亚胺，环氧树脂或硅树脂）。 该膜适于吸收可见光和紫外线波长的光，对吸湿不敏感，并在芯片上施加热机械应力，使得该应力至少部分地中和芯片组装后由外部部分施加的应力。

公开(公告)号：US06716674B2

公开(公告)日：2004-04-06

申请号：US09952038

申请日：2001-09-11

申请人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

发明人： Kiyoshi Yajima ,  Mutsumi Masumoto ,  Chihiro Hatano ,  Kimitaka Nishio ,  Noriyuki Kirikae

IPC分类号： H01L2144

CPC分类号： H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/45144 ,  H01L2224/83191 ,  H01L2224/83805 ,  H01L2224/83855 ,  H01L2224/85207 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 &mgr;m or thicker. A semiconductor device made by this method and a wafer for use with this method.

摘要翻译： 一种半导体封装件的制造方法，其特征在于，在形成有许多半导体器件的晶片的背面设置有由单层膜热固接合而形成的接合层的步骤，将切割带贴合在其接合层侧， 同时切割接合层和晶片以获得具有接合层的半导体器件，并且其中具有接合层的半导体器件与切割带分离并且模具附接到作为其的主体的插入基板的步骤 他们是保税的 其中，上述膜热固性粘合剂含有环氧树脂，环氧树脂固化剂和苯氧基树脂以及50〜80重量％的球形二氧化硅，并且接合层为100μm以上。 通过该方法制造的半导体器件和用于该方法的晶片。

公开(公告)号：US08298947B2

公开(公告)日：2012-10-30

申请号：US12917620

申请日：2010-11-02

申请人： Mutsumi Masumoto

发明人： Mutsumi Masumoto

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L23/3128 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32507 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73204 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/8383 ,  H01L2224/85205 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/0102 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  H05K1/189 ,  H05K3/244 ,  H05K3/328 ,  H05K3/3463 ,  H05K2201/10674 ,  H05K2203/0285 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/83205

摘要： A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 μm thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 μm thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 μm thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

摘要翻译： 半导体器件具有芯片（101），其具有组装在带基板（102）上的金柱（212），其具有用于附接到外部部件的焊球（103）。 带衬底（约30至70μm厚）在其第一表面上具有由约0.04至0.12μm厚度的连续薄镍层（222）覆盖的第一铜接触焊盘（221）。 包括螺柱（212）的金属与镍接触。 在第二基板表面上是由包括金，铜/锡合金和铜/镍/锡合金的合金层（约2至3μm厚）覆盖的第二铜接触焊盘（231） 该合金冶金地附接到第二铜焊盘并基本上不含非合金镍。 包括锡的回流体（103）冶金地附接到每个第二焊盘的合金层。