公开(公告)号：US08735219B2

公开(公告)日：2014-05-27

申请号：US13599023

申请日：2012-08-30

申请人： Paul M. Enquist ,  Gaius Gillman Fountain

发明人： Paul M. Enquist ,  Gaius Gillman Fountain

IPC分类号： H01L21/48

CPC分类号： H01L25/0657 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83053 ,  H01L2224/83201 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

摘要翻译： 一种将具有第一表面的第一衬底与第一绝缘材料和第一接触结构与具有第二表面的第二衬底与第二绝缘材料和第二接触结构集成的方法。 第一绝缘材料直接接合到第二绝缘材料上。 去除第一衬底的一部分以留下剩余部分。 具有与第一基板的CTE基本相同的热膨胀系数（CTE）的第三基板被结合到剩余部分。 粘合的基底被加热以促进第一和第二接触结构之间的电接触。 在加热之后移除第三衬底以提供具有可靠电接触的接合结构。

公开(公告)号：US08426248B2

公开(公告)日：2013-04-23

申请号：US12913385

申请日：2010-10-27

申请人： Qin-Yi Tong ,  Paul M. Enquist ,  Anthony Scot Rose

发明人： Qin-Yi Tong ,  Paul M. Enquist ,  Anthony Scot Rose

IPC分类号： H01L21/00

摘要： A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

公开(公告)号：US08389378B2

公开(公告)日：2013-03-05

申请号：US12270585

申请日：2008-11-13

申请人： Paul M. Enquist ,  Gaius Gillman Fountain, Jr. ,  Qin-Yi Tong

发明人： Paul M. Enquist ,  Gaius Gillman Fountain, Jr. ,  Qin-Yi Tong

IPC分类号： H01L31/102

CPC分类号： H01L21/76838 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/0401 ,  H01L2224/81121 ,  H01L2224/81201 ,  H01L2224/8123 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2224/81931 ,  H01L2224/83894 ,  H01L2224/9202 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01059 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/81

摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

公开(公告)号：US20080150153A1

公开(公告)日：2008-06-26

申请号：US12045555

申请日：2008-03-10

申请人： Paul M. ENQUIST

发明人： Paul M. ENQUIST

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L25/0657 ,  H01L21/76805 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68354 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2924/01015 ,  H01L2924/01031

摘要： A method of connecting elements such as semiconductor devices and a device having connected elements such as semiconductor devices. A first element having a first contact structure is bonded to a second element having a second contact structure. A single mask is used to form a via in the first element to expose the first contact and the second contact. The first contact structure is used as a mask to expose the second contact structure. A contact member is formed in contact with the first and second contact structures. The first contact structure may have an aperture or gap through which the first and second contact structures are connected. A back surface of the first contact structure may be exposed by the etching.

摘要翻译： 连接诸如半导体器件的元件和具有诸如半导体器件的连接元件的器件的方法。 具有第一接触结构的第一元件被结合到具有第二接触结构的第二元件。 使用单个掩模在第一元件中形成通孔以暴露第一触点和第二触点。 第一接触结构用作掩模以暴露第二接触结构。 接触构件形成为与第一和第二接触结构接触。 第一接触结构可以具有孔或间隙，第一和第二接触结构通过该孔或间隙连接。 第一接触结构的后表面可能被蚀刻暴露。

公开(公告)号：US06984571B1

公开(公告)日：2006-01-10

申请号：US09410054

申请日：1999-10-01

申请人： Paul M. Enquist

发明人： Paul M. Enquist

IPC分类号： H01L29/06

CPC分类号： H01L24/08 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/13 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/26 ,  H01L24/27 ,  H01L24/30 ,  H01L24/48 ,  H01L24/80 ,  H01L24/82 ,  H01L24/83 ,  H01L24/94 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/167 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/14634 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0807 ,  H01L2224/08123 ,  H01L2224/1134 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/3005 ,  H01L2224/30104 ,  H01L2224/305 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/80896 ,  H01L2224/81894 ,  H01L2224/8303 ,  H01L2224/83092 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/83193 ,  H01L2224/83345 ,  H01L2224/83359 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83912 ,  H01L2224/83948 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  Y10S148/012 ,  Y10S438/977 ,  H01L2224/13099 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/80001 ,  H01L2224/82

摘要： A device integration method and integrated device. The method includes the steps of polishing surfaces of first and second workpieces each to a surface roughness of about 5–10 Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1–10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.

公开(公告)号：US08524533B2

公开(公告)日：2013-09-03

申请号：US12913385

申请日：2010-10-27

申请人： Qin-Yi Tong ,  Paul M. Enquist ,  Anthony Scot Rose

发明人： Qin-Yi Tong ,  Paul M. Enquist ,  Anthony Scot Rose

IPC分类号： H01L21/00

CPC分类号： H01L21/76251 ,  B23K20/02 ,  H01L21/481 ,  H01L24/09 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/89 ,  H01L24/90 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/80801 ,  H01L2224/81011 ,  H01L2224/81013 ,  H01L2224/81014 ,  H01L2224/81136 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/8121 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8183 ,  H01L2224/81894 ,  H01L2224/83095 ,  H01L2224/8319 ,  H01L2224/8334 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83907 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01003 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/351 ,  Y10T29/49126 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05124 ,  H01L2224/05147

摘要： A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

公开(公告)号：US08053329B2

公开(公告)日：2011-11-08

申请号：US12493957

申请日：2009-06-29

申请人： Qin-Yi Tong ,  Gaius Gillman Fountain, Jr. ,  Paul M. Enquist

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, Jr. ,  Paul M. Enquist

IPC分类号： H01L21/48

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

摘要翻译： 在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。 该方法还可以包括除去界面聚合的副产物以防止反向聚合反应，以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。 要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。 表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。 蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。

公开(公告)号：US07956447B2

公开(公告)日：2011-06-07

申请号：US10792757

申请日：2004-03-05

申请人： Paul M. Enquist ,  Gaius G. Fountain, Jr. ,  Carl T. Petteway

发明人： Paul M. Enquist ,  Gaius G. Fountain, Jr. ,  Carl T. Petteway

IPC分类号： H01L23/02

CPC分类号： H01L21/67333 ,  H01L2924/0002 ,  Y10S414/135 ,  Y10S414/14 ,  Y10S414/141 ,  H01L2924/00

摘要： A waffle pack device including a member having recesses in a surface of the member to accommodate die from at least one semiconductor wafer. The member is compatible with semiconductor wafer handling equipment and/or semiconductor wafer processing. Preferably, the member accommodates at least a majority of die from a semiconductor wafer. Further, one semiconductor device assembly method is provided which removes die from a singular waffle pack device, places die from the single waffle pack device on a semiconductor package to assemble from the placed die all die components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit. Another semiconductor device assembly method is provided which removes die from at least one waffle pack device, places die from the at least one waffle pack device on a semiconductor package to assemble from the placed die device components required for an integrated circuit, and electrically interconnects the placed die in the semiconductor package to form the integrated circuit.

摘要翻译： 一种华夫饼包装置，包括在所述构件的表面中具有凹部以容纳来自至少一个半导体晶片的模具的构件。 该元件与半导体晶片处理设备和/或半导体晶片处理兼容。 优选地，构件容纳来自半导体晶片的至少大部分管芯。 此外，提供了一种半导体器件组装方法，其从单个华夫饼包装置中去除裸片，将来自单个华夫饼包装置的管芯放置在半导体封装上，以从放置的管芯组装集成电路所需的所有管芯部件，并将 放置在半导体封装中以形成集成电路。 提供了另一种半导体器件组装方法，其从至少一个华夫饼包装置去除管芯，将来自至少一个华夫饼包装置的管芯放置在半导体封装上，以从集成电路所需的放置的管芯器件组件中组装，并将 放置在半导体封装中以形成集成电路。

公开(公告)号：US07781307B2

公开(公告)日：2010-08-24

申请号：US12493957

申请日：2009-06-29

申请人： Qin-Yi Tong ,  Gaius Gillman Fountain, Jr. ,  Paul M. Enquist

发明人： Qin-Yi Tong ,  Gaius Gillman Fountain, Jr. ,  Paul M. Enquist

IPC分类号： H01L21/48

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

公开(公告)号：US20100163169A1

公开(公告)日：2010-07-01

申请号：US12720368

申请日：2010-03-09

申请人： Qin-Yi TONG ,  Gaius Gillman FOUNTAIN, JR. ,  Paul M. ENQUIST

发明人： Qin-Yi TONG ,  Gaius Gillman FOUNTAIN, JR. ,  Paul M. ENQUIST

IPC分类号： B32B38/10

CPC分类号： H01L24/83 ,  H01L21/0206 ,  H01L21/2007 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/76251 ,  H01L24/26 ,  H01L24/75 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/085 ,  H01L29/06 ,  H01L29/16 ,  H01L2224/8301 ,  H01L2224/8303 ,  H01L2224/83031 ,  H01L2224/8309 ,  H01L2224/83099 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/83894 ,  H01L2224/83896 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01084 ,  H01L2924/01093 ,  H01L2924/0132 ,  H01L2924/05442 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  Y10S148/012 ,  Y10S438/974 ,  Y10T156/10 ,  Y10T156/1043 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00

摘要： A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.

摘要翻译： 在低温或室温下接合的方法包括通过清洗或蚀刻进行表面清洁和活化的步骤。 该方法还可以包括除去界面聚合的副产物以防止反向聚合反应，以允许诸如硅，氮化硅和SiO 2的材料的室温化学键合。 要结合的表面被抛光到高度的平滑度和平坦度。 VSE可以使用反应离子蚀刻或湿蚀刻来稍微蚀刻被结合的表面。 表面粗糙度和平面度不会降低，并且可以通过VSE工艺增强。 蚀刻的表面可以在诸如氢氧化铵或氟化铵的溶液中冲洗以促进在表面上形成所需的粘结物质。