公开(公告)号：US20060249854A1

公开(公告)日：2006-11-09

申请号：US11478933

申请日：2006-06-29

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05655 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14

摘要： A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

摘要翻译： 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。

公开(公告)号：US20050167837A1

公开(公告)日：2005-08-04

申请号：US10707892

申请日：2004-01-21

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Sarah Knickerbocker ,  Samuel McKnight ,  Kevin Petrarca ,  Kamalesh Srivastava ,  Roger Quon

IPC分类号： H01L23/485 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L22/32 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05655 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14

摘要： A durable chip pad for integrated circuit (IC) chips, semiconductor wafer with IC chips with durable chip pads in a number of die locations and a method of making the IC chips on the wafer. The chip may be probed for performance testing with the probe contacting the durable chip pads directly.

摘要翻译： 用于集成电路（IC）芯片的耐用芯片焊盘，具有在多个芯片位置具有耐用芯片焊盘的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 可以通过探头直接接触耐用的芯片焊盘来探测芯片进行性能测试。

公开(公告)号：US20050062170A1

公开(公告)日：2005-03-24

申请号：US10666775

申请日：2003-09-18

申请人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

发明人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/44 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

摘要翻译： 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，该导电焊盘与覆盖该焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。

公开(公告)号：US20060081981A1

公开(公告)日：2006-04-20

申请号：US11271760

申请日：2005-11-10

申请人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

发明人： Julie Biggs ,  Tien-Jen Cheng ,  David Eichstadt ,  Lisa Fanti ,  Jonathan Griffith ,  Randolph Knarr ,  Sarah Knickerbocker ,  Kevin Petrarca ,  Roger Quon ,  Wolfgang Sauter ,  Kamalesh Srivastava ,  Richard Volant

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

公开(公告)号：US20050026416A1

公开(公告)日：2005-02-03

申请号：US10604578

申请日：2003-07-31

申请人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Kevin Petrarca ,  Roger Quon

发明人： Tien-Jen Cheng ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Kevin Petrarca ,  Roger Quon

IPC分类号： H01L21/60 ,  H01L21/44 ,  H01L23/48 ,  H05K3/34 ,  H05K3/40

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/03622 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13076 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H05K3/3457 ,  H05K3/4007 ,  H01L2224/05099

摘要： A solder bump for bonding an electronic device to a substrate or another structure is formed by plating a high aspect ratio copper pin on a supporting structure, encapsulating the pin in a barrier material, plating a solder on the barrier material and then reflowing the solder.

摘要翻译： 通过在支撑结构上镀覆高纵横比的铜针，将该引脚封装在阻挡材料中，将焊料电镀在阻挡材料上，然后回流焊料，形成用于将电子器件接合到衬底或其它结构的焊料凸块。

公开(公告)号：US20050121803A1

公开(公告)日：2005-06-09

申请号：US11030496

申请日：2005-01-06

申请人： David Angell ,  Frederic Beaulieu ,  Takashi Hisada ,  Adreanne Kelly ,  Samuel McKnight ,  Hiromitsu Miyai ,  Kevin Petrarca ,  Wolfgang Sauter ,  Richard Volant ,  Caitlin Weinstein

发明人： David Angell ,  Frederic Beaulieu ,  Takashi Hisada ,  Adreanne Kelly ,  Samuel McKnight ,  Hiromitsu Miyai ,  Kevin Petrarca ,  Wolfgang Sauter ,  Richard Volant ,  Caitlin Weinstein

IPC分类号： H01L23/485 ,  H01L21/44 ,  H01L23/48 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/00

摘要： Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so as to form nonplanar metallic structures. Surrounding each of the nonplanar metallic structures is a ring of dielectric material which provides a hard stop during probing of the bond pad so as to limit the amount of bond pad that can be removed during probing.

摘要翻译： 公开了一种具有非平面电介质结构和在非平面电介质结构上共形形成的金属接合层的增强接合焊盘结构。 非平面电介质结构基本上在金属接合层中再现，从而形成非平面金属结构。 围绕非平面金属结构的每一个是介电材料环，其在接合焊盘探测期间提供硬停止，以限制在探测期间可以去除的接合焊盘的量。

公开(公告)号：US07485964B2

公开(公告)日：2009-02-03

申请号：US11399579

申请日：2006-04-06

申请人： John M. Cotte ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Kevin Petrarca ,  John P. Simons ,  Charles J. Taft ,  Richard Volant

发明人： John M. Cotte ,  Kenneth John McCullough ,  Wayne Martin Moreau ,  Kevin Petrarca ,  John P. Simons ,  Charles J. Taft ,  Richard Volant

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02118 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/249978 ,  Y10T428/24999 ,  H01L2924/00

摘要： A dielectric material formed by contacting a low dielectric constant polymer with liquid or supercritical carbon dioxide, under thermodynamic conditions which maintain the carbon dioxide in the liquid or supercritical state, wherein a porous product is formed. Thereupon, thermodynamic conditions are changed to ambient wherein carbon dioxide escapes from the pores and is replaced with air.

摘要翻译： 在将二氧化碳保持在液态或超临界状态的热力学条件下，通过使低介电常数聚合物与液体或超临界二氧化碳接触而形成的电介质材料，其中形成多孔产品。 因此，热力学条件改变为环境，其中二氧化碳从孔中逸出并被空气替代。

公开(公告)号：US20060124927A1

公开(公告)日：2006-06-15

申请号：US10905013

申请日：2004-12-09

申请人： Robert Groves ,  Peter Gruber ,  Kevin Petrarca ,  Richard Volant ,  George Walker

发明人： Robert Groves ,  Peter Gruber ,  Kevin Petrarca ,  Richard Volant ,  George Walker

IPC分类号： H01L21/66 ,  H01L23/58

CPC分类号： H05K3/3468 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K3/325 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K2203/162 ,  H05K2203/167 ,  H01L2224/0401

摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

摘要翻译： 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。

公开(公告)号：US20100210098A1

公开(公告)日：2010-08-19

申请号：US12372174

申请日：2009-02-17

申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

IPC分类号： H01L21/283

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。

公开(公告)号：US20070181974A1

公开(公告)日：2007-08-09

申请号：US11307404

申请日：2006-02-06

申请人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

发明人： Douglas Coolbaugh ,  Timothy Dalton ,  Daniel Edelstein ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Kevin Petrarca ,  Anthony Stamper ,  Richard Volant

IPC分类号： H01L29/00 ,  H01L21/20

CPC分类号： H01L28/20 ,  H01L23/5228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.

摘要翻译： 公开了避免半导体器件小型化的问题的电阻器及相关方法。 在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。 在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。 这两个实施方案可以单独使用或一起使用。 还公开了用于产生电阻器的相关方法。