Passivation structure for semiconductor devices
    2.
    发明申请
    Passivation structure for semiconductor devices 审中-公开
    半导体器件钝化结构

    公开(公告)号:US20060138668A1

    公开(公告)日:2006-06-29

    申请号:US11023296

    申请日:2004-12-27

    IPC分类号: H01L23/06

    摘要: A system and method for providing a passivation structure for semiconductor devices is provided. In an embodiment, the passivation structure comprises a first barrier layer and a second barrier layer, wherein the second barrier layer may comprise a material, such as cobalt and/or nickel, that is less pure than the first barrier layer. In another embodiment, a single gradient barrier layer is formed. In this embodiment the single gradient barrier layer exhibits a greater pure conductive material, such as cobalt and/or nickel, nearer the conductive line than near the surface.

    摘要翻译: 提供了一种用于提供半导体器件的钝化结构的系统和方法。 在一个实施例中,钝化结构包括第一阻挡层和第二阻挡层,其中第二阻挡层可以包括比第一阻挡层更纯的材料,例如钴和/或镍。 在另一个实施例中,形成单个梯度阻挡层。 在该实施例中,单个梯度阻挡层表现出比在表面附近更靠近导电线的较高纯度的导电材料,例如钴和/或镍。

    ELECTROPLATING ADDITIVE FOR IMPROVED RELIABILITY
    4.
    发明申请
    ELECTROPLATING ADDITIVE FOR IMPROVED RELIABILITY 审中-公开
    电解添加剂改善可靠性

    公开(公告)号:US20060243599A1

    公开(公告)日:2006-11-02

    申请号:US10908143

    申请日:2005-04-28

    IPC分类号: C25D3/00

    CPC分类号: C25D3/02 C25D3/38

    摘要: Described are methods of and compositions for electrodepositing copper or other metals onto interconnects of a semiconductor substrate from an electroplating composition containing at least one nitrogen-containing additive. The nitrogen-containing additive has a molecular weight of between 10 and 1000, a concentration of between 5.0 and 10.0 milligrams per liter of the electroplating composition. The methods and compositions result in electroplated copper interconnects that have smooth surfaces that are relatively free of pits and humps.

    摘要翻译: 描述了从含有至少一种含氮添加剂的电镀组合物将铜或其它金属电沉积在半导体衬底的互连上的方法和组合物。 含氮添加剂的分子量为10至1000,每升电镀组合物的浓度为5.0至10.0毫克。 这些方法和组合物导致电镀铜互连具有相对没有凹坑和凸起的光滑表面。

    Electroplating composition and method
    5.
    发明申请
    Electroplating composition and method 审中-公开
    电镀组合物及方法

    公开(公告)号:US20060213780A1

    公开(公告)日:2006-09-28

    申请号:US11087494

    申请日:2005-03-24

    IPC分类号: C25D3/38 C25D3/00

    CPC分类号: C25D7/123 C25D3/02 C25D3/38

    摘要: Electroplating composition and method. In one embodiment, the composition comprises an electrolyte solution and an amine-based copolymer comprising monomer units of ethylene oxide and propylene oxide, with the propylene oxide present in a quantity of at least about 70 wt %. The method comprises electroplating a metal onto a substrate from the electroplating composition of the invention.

    摘要翻译: 电镀组合物及方法。 在一个实施方案中,组合物包含电解质溶液和包含环氧乙烷和环氧丙烷的单体单元的胺基共聚物,其中环氧丙烷的存在量为至少约70重量%。 该方法包括从本发明的电镀组合物将金属电镀到基底上。

    Uniform passivation method for conductive features
    6.
    发明申请
    Uniform passivation method for conductive features 有权
    导电特性均匀钝化方法

    公开(公告)号:US20060172529A1

    公开(公告)日:2006-08-03

    申请号:US11047836

    申请日:2005-02-01

    IPC分类号: H01L21/465 H01L23/52

    摘要: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

    摘要翻译: 在导电特征上形成钝化层之前,用处理溶液处理导电特征的顶表面。 处理溶液包括清洗溶液和化学接枝前体。 处理溶液还可以包括流平和润湿剂以改善化学接枝前体的覆盖均匀性。 该方法导致在工件的表面上的导电特征上形成均匀的钝化层。

    Silicide structure for ultra-shallow junction for MOS devices
    7.
    发明授权
    Silicide structure for ultra-shallow junction for MOS devices 有权
    用于MOS器件的超浅结的硅化物结构

    公开(公告)号:US07332435B2

    公开(公告)日:2008-02-19

    申请号:US11072038

    申请日:2005-03-04

    IPC分类号: H01L21/44

    摘要: A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

    摘要翻译: 一种形成半导体器件的方法,包括:在沟道区上形成栅介电层; 在所述栅极电介质层上形成栅电极; 形成与所述栅电极的各个边缘基本对准的源极/漏极区域,其间具有沟道区域; 在源/漏区上形成薄金属层; 在所述薄金属层上形成金属合金层; 并将薄金属层转变成低电阻金属硅化物。

    Novel silicide structure for ultra-shallow junction for MOS devices
    10.
    发明申请
    Novel silicide structure for ultra-shallow junction for MOS devices 有权
    用于MOS器件的超浅结的新型硅化物结构

    公开(公告)号:US20060205214A1

    公开(公告)日:2006-09-14

    申请号:US11072038

    申请日:2005-03-04

    IPC分类号: H01L21/44

    摘要: A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

    摘要翻译: 一种形成半导体器件的方法,包括:在沟道区上形成栅介电层; 在所述栅极电介质层上形成栅电极; 形成与所述栅电极的各个边缘基本对准的源极/漏极区域,其间具有沟道区域; 在源/漏区上形成薄金属层; 在所述薄金属层上形成金属合金层; 并将薄金属层转变成低电阻金属硅化物。