公开(公告)号：US08962392B2

公开(公告)日：2015-02-24

申请号：US13418868

申请日：2012-03-13

申请人： Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

发明人： Chin-Fu Kao ,  Jing-Cheng Lin ,  Jui-Pin Hung ,  Szu Wei Lu

IPC分类号： H01L21/50 ,  H01L21/56

CPC分类号： H01L21/563 ,  H01L21/568 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method includes bonding a carrier over a top die. The method further includes curing an underfill disposed between a substrate and the top die. The method further includes applying a force over the carrier during the curing. The method further includes removing the carrier from the top die.

摘要翻译： 一种方法包括将载体粘合在顶模上。 该方法还包括固化设置在基底和顶模之间的底部填充物。 该方法还包括在固化期间在载体上施加力。 该方法还包括从顶模移除载体。

公开(公告)号：US09064879B2

公开(公告)日：2015-06-23

申请号：US13228244

申请日：2011-09-08

申请人： Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

发明人： Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/56 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

摘要： Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.

摘要翻译： 公开了利用新颖的芯片附着膜的半导体器件的封装方法和结构。 在一个实施例中，封装半导体器件的方法包括提供载体晶片并且在载体晶片上形成包括聚合物的管芯附着膜（DAF）。 多个模具附接到DAF，并且多个管芯被封装。 至少载体晶片从封装的管芯移除，并且封装的管芯被切割。

公开(公告)号：US20130062760A1

公开(公告)日：2013-03-14

申请号：US13228244

申请日：2011-09-08

申请人： Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

发明人： Jui-Pin Hung ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Chin-Chuan Chang ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Chin-Fu Kao ,  Yi-Chao Mao ,  Szu Wei Lu

IPC分类号： H01L23/498 ,  H01L21/60 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/11002 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552 ,  H01L2924/00

摘要： Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated.

摘要翻译： 公开了利用新颖的芯片附着膜的半导体器件的封装方法和结构。 在一个实施例中，封装半导体器件的方法包括提供载体晶片并且在载体晶片上形成包括聚合物的管芯附着膜（DAF）。 多个模具附接到DAF，并且多个管芯被封装。 至少载体晶片从封装的管芯移除，并且封装的管芯被切割。

公开(公告)号：US08779599B2

公开(公告)日：2014-07-15

申请号：US13298126

申请日：2011-11-16

申请人： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

摘要： A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

摘要翻译： 一种器件包括底部芯片和结合到底部芯片的有源顶部管芯。 虚设裸片连接到底部芯片。 虚设裸片与底部芯片电绝缘。

公开(公告)号：US20130037990A1

公开(公告)日：2013-02-14

申请号：US13208197

申请日：2011-08-11

申请人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/56

CPC分类号： H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

摘要翻译： 模制系统的底部追逐和顶部追逐形成容纳模制载体和一个或多个装置的空腔。 模制载体被放置在由引导部件限定的期望位置。 引导部件可以完全在腔内，或者延伸到底部追逐的表面之上，并延伸到顶部追逐和底部追逐的接触边缘上，使得在顶部追逐的边缘和边缘之间存在间隙 由模制材料填充以覆盖模制载体的边缘的模制载体。 释放部件可以与顶部追逐和/或底部追逐相关联，其可以是具有释放膜的多个带辊或底部追逐内的多个真空孔，或者具有底部追逐的多个底部销 。

公开(公告)号：US20130075892A1

公开(公告)日：2013-03-28

申请号：US13246553

申请日：2011-09-27

申请人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Ying-Ching Shih ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/48 ,  H01L21/50

CPC分类号： H01L23/48 ,  H01L21/6835 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

摘要： A method for fabricating three dimensional integrated circuits comprises providing a wafer stack wherein a plurality of semiconductor dies are mounted on a first semiconductor die, forming a molding compound layer on the first side of the first semiconductor die, wherein the plurality of semiconductor dies are embedded in the molding compound layer. The method further comprises grinding a second side of the first semiconductor die until a plurality of through vias become exposed, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

摘要翻译： 一种用于制造三维集成电路的方法包括：提供其中多个半导体管芯安装在第一半导体管芯上的晶片堆叠，在第一半导体管芯的第一侧上形成模塑料层，其中多个半导体管芯被嵌入 在模塑料层中。 该方法还包括研磨第一半导体管芯的第二面直到多个通孔露出，将晶片堆叠附着到带框架上并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US20130119552A1

公开(公告)日：2013-05-16

申请号：US13298126

申请日：2011-11-16

申请人： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L23/538 ,  H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

摘要： A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

摘要翻译： 一种器件包括底部芯片和结合到底部芯片的有源顶部管芯。 虚设裸片连接到底部芯片。 虚设裸片与底部芯片电绝缘。

公开(公告)号：US09679783B2

公开(公告)日：2017-06-13

申请号：US13208197

申请日：2011-08-11

申请人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Chin-Chuan Chang ,  Jui-Pin Hung ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： B29C33/12 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L21/561 ,  B29C33/123 ,  H01L21/566 ,  H01L23/3121 ,  H01L24/96 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00

摘要： A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

公开(公告)号：US09418876B2

公开(公告)日：2016-08-16

申请号：US13224575

申请日：2011-09-02

申请人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

发明人： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

摘要： A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

摘要翻译： 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US08580683B2

公开(公告)日：2013-11-12

申请号：US13246556

申请日：2011-09-27

申请人： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

发明人： Chung Yu Wang ,  Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC分类号： H01L23/28

CPC分类号： H01L21/78 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029

摘要： Methods and apparatus for performing molding on die on wafer interposers. A method includes receiving an interposer assembly having a die side and an opposite side including two or more integrated circuit dies mounted on the die side of the interposer, the interposer assembly having spaces formed on the die side of the interposer between the two or more integrated circuit dies; mounting at least one stress relief feature on the die side of the interposer assembly in one of the spaces between the two or more integrated circuit dies; and molding the integrated circuit dies using a mold compound, the mold compound surrounding the two or more integrated circuit dies and the at least one stress relief feature. An apparatus is disclosed having integrated circuits mounted on a die side of an interposer, stress relief features between the integrated circuits and mold compound over the integrated circuits.

摘要翻译： 用于在晶片插入件上的模具上进行模制的方法和装置。 一种方法包括接收具有管芯侧面和相对侧的插入件组件，所述插入件组件包括安装在所述插入件的裸片侧上的两个或多个集成电路管芯，所述插入器组件具有形成在所述插入件的裸片侧上的两个或更多个集成 电路模具; 在所述两个或更多个集成电路管芯之间的空间之一中在所述插入器组件的管芯侧上安装至少一个应力释放特征; 以及使用模具化合物模制所述集成电路模具，围绕所述两个或更多个集成电路管芯的所述模具化合物以及所述至少一个应力释放特征。 公开了一种装置，其集成电路安装在插入件的裸片侧，集成电路之间的应力消除特征和集成电路上的模具化合物。