公开(公告)号：US5869889A

公开(公告)日：1999-02-09

申请号：US840614

申请日：1997-04-21

申请人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

IPC分类号： H01L23/29 ,  H01L21/60 ,  H01L23/12 ,  H01L23/24 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498 ,  H01L23/34

CPC分类号： H01L23/36 ,  H01L23/24 ,  H01L23/4985 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181

摘要： An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.

摘要翻译： 集成电路封装包括散热器，其形成为在平面之间具有居中设置的凹部，以及从平面延伸到中心设置表面的柔性带。 半导体芯片安装在柔性带之间的中央布置的表面上，并且引线将芯片上的接合焊盘互连到柔性带上的金属互连图案。 然后施加塑料模制或环氧树脂以将芯片和引线接合封装在散热器的中心设置的平坦表面中。 然后使用焊球将封装容易地安装在母板上。

公开(公告)号：US06297550B1

公开(公告)日：2001-10-02

申请号：US09053357

申请日：1998-04-01

申请人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

IPC分类号： H01L2334

CPC分类号： H01L23/10 ,  H01L23/053 ,  H01L23/36 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/49109 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor package (100) includes a bondable aluminum heatspreader (130) made from anodized aluminum, thereby forming an anodization layer (132) on the surface of the heatspreader. Portions of the anodization layer are removed, e.g., by grinding, in order to provide an attachment area (124) to which a wire (122) or beam may be bonded in order to electrically connect the heatspreader to a desired voltage potential, such as a ground potential or a positive or negative potential. The heatspreader is thermally bonded to a semiconductor die (102) housed within the package. The anodized aluminum heatspreader thus not only removes and dissipates heat from the semiconductor die, but also functions as a voltage or ground plane within the semiconductor package.

摘要翻译： 半导体封装（100）包括由阳极化铝制成的可粘合铝散热器（130），从而在散热器的表面上形成阳极氧化层（132）。 阳极氧化层的一部分例如通过研磨被去除，以便提供可以将导线（122）或梁结合到其上的附接区域（124），以将散热器电连接到期望的电压电位，例如 地电位或正或负电位。 散热器热粘合到容纳在封装内的半导体管芯（102）。 因此，阳极氧化铝散热器不仅能够从半导体管芯移除和散发热量，而且可用作半导体封装内的电压或接地平面。

公开(公告)号：US5841198A

公开(公告)日：1998-11-24

申请号：US837685

申请日：1997-04-21

申请人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

IPC分类号： H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/613

摘要： A ball grid array package utilizes solder balls having central cores of a material with a higher melting point than solder material surrounding the core. When the ball grid package and motherboard assembly are heated to the melting point of the solder material, the cores remain solid and function as spacers in preventing direct contact of the package surface and the motherboard surface, thus preventing molten solder from being squashed and flowing to adjacent ball contacts.

摘要翻译： 球栅阵列封装使用具有比包围芯的焊料更高的熔点的材料的中心芯的焊球。 当球栅包装和母板组件被加热到焊料材料的熔点时，芯保持固体并且用作间隔件，以防止封装表面和母板表面的直接接触，从而防止熔融焊料被挤压并流动到 相邻球接触。

公开(公告)号：US6110815A

公开(公告)日：2000-08-29

申请号：US103291

申请日：1998-06-23

申请人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Patrick Variot ,  Maniam Alagaratnam

IPC分类号： H01L21/48 ,  H05K3/24 ,  H01L21/44

CPC分类号： H01L21/4846 ,  H05K3/241

摘要： A method of electroplating a high density integrated circuit (IC) substrate using a conductive elastomer including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces with conductive trace lands formed on its surface. Covering only the traces (not the trace lands) with a plating resist and exposing portions of the conductive traces. Inserting the IC substrate into a electroplating fixture. Engaging a conductive elastomer to the IC substrate, covering the plurality of conductive traces and electrically connecting all of the traces together. Electroplating the trace lands on the IC substrate with conductive material (such as gold or nickel) by using the conductive elastomer as the electrical connection to the trace lands (via the exposed metal traces). Disengaging the conductive elastomer after electroplating is finished and removing the IC substrate from the electroplating fixture.

摘要翻译： 一种使用导电弹性体对高密度集成电路（IC）衬底进行电镀的方法，包括以下步骤：提供由非导电材料制成的IC衬底，该IC衬底具有形成在其表面上的导电迹线的多个导电迹线。 仅覆盖具有电镀抗蚀剂的痕迹（而不是痕迹），并暴露部分导电迹线。 将IC基板插入电镀夹具。 将导电弹性体接合到IC基板，覆盖多个导电迹线并将所有迹线电连接在一起。 通过使用导电弹性体作为与轨迹的电连接（通过暴露的金属迹线），用导电材料（例如金或镍）将迹线焊盘电镀在IC基板上。 完成电镀后的导电弹性体脱模，并从电镀夹具中取出IC基片。

公开(公告)号：US5923047A

公开(公告)日：1999-07-13

申请号：US837618

申请日：1997-04-21

申请人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

IPC分类号： G01R31/28 ,  H01L21/301 ,  H01L23/485 ,  H01L23/58 ,  H01L21/60 ,  H01L21/66

CPC分类号： H01L24/06 ,  H01L22/32 ,  G01R31/2884 ,  H01L2224/05553 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/14

摘要： The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.

摘要翻译： 通过在相邻的管芯之间的刻划空间中提供多个测试焊盘，通过有效地增加每个管芯上相邻的输入/输出焊盘之间的间距，有助于半导体晶片中以行和列布置的多个管芯中的集成电路的测试。 替代的测试焊盘与相邻裸片上的替代焊盘相连，从而有效地增加相邻裸片的间距以进行测试。 在对集成电路进行测试并且标记故障电路之后，在刻划空间刻划晶片并断开晶片以恢复单独的芯片或集成电路芯片。

公开(公告)号：US5927505A

公开(公告)日：1999-07-27

申请号：US920430

申请日：1997-08-29

申请人： Chok J. Chia ,  Seng-Sooi Lim ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Seng-Sooi Lim ,  Maniam Alagaratnam

IPC分类号： B29C45/14 ,  H01L21/56 ,  H01L23/31 ,  B65D73/02 ,  H01L23/04

CPC分类号： B29C45/14418 ,  B29C45/14655 ,  H01L21/565 ,  H01L23/3121 ,  B29C2045/14934 ,  B29C70/72 ,  B29C70/78 ,  H01L2924/0002

摘要： Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.

摘要翻译： 具有宽范围厚度并且旨在用塑料封装体包覆成型的基板容纳在共同的模具中。 衬底的顶表面设置有坝结构，其可以在衬底上形成为附加层，并且其优选地为正方形环的形式。 槽（通道）被加工（例如通过路由）到坝结构的表面中。 具有用于形成封装主体的空腔的顶部模具半部在空腔的周边处设置有密封结构。 密封结构具有嵌入坝结构通道的脊。 容易调节坝结构中槽的深度，以确保上模半部在基板上的均匀夹紧压力，使得液体模塑料被包含在空腔内，从而不会对衬底施加过大的压力。

公开(公告)号：US06429534B1

公开(公告)日：2002-08-06

申请号：US09478972

申请日：2000-01-06

申请人： Qwai H. Low ,  Chok J. Chia ,  Maniam Alagaratnam

发明人： Qwai H. Low ,  Chok J. Chia ,  Maniam Alagaratnam

IPC分类号： H01L2348

CPC分类号： H01L23/49827 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided is an interposer tape which provides electrical communication between a die and a packaging substrate. The dimensions of the interposer tape may vary to accommodate a variety of die sizes for the same packaging substrate. The interposer tape includes an array of traces. A first set of wire bonds is formed between the array of traces and the die. A second set of wire bonds is formed between the array of traces and the packaging substrate.

摘要翻译： 提供了一种提供管芯和封装衬底之间的电连通的插入器带。 插入器带的尺寸可以变化以适应相同封装基板的各种管芯尺寸。 插入器带包括一列迹线。 在迹线阵列和模具之间形成第一组引线键合。 在迹线阵列和封装衬底之间形成第二组线接合。

公开(公告)号：US6081997A

公开(公告)日：2000-07-04

申请号：US911418

申请日：1997-08-14

申请人： Chok J. Chia ,  Seng Sooi Lim ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Seng Sooi Lim ,  Maniam Alagaratnam

IPC分类号： H01L21/56 ,  H05K3/30

CPC分类号： H01L21/565 ,  H01L2224/16 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/18161 ,  Y10T29/49121 ,  Y10T29/49144 ,  Y10T29/49146

摘要： A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant. The liquid encapsulant is preferably a C4 underfill material. By injecting the liquid encapsulant under pressure, the amount of time required to dispense the liquid encapsulant is reduced as well as the number of voids present in the liquid encapsulant. Following at least partial curing of the encapsulant, the mold sections are separated, and the packaged semiconductor device is removed. When fully cured and hardened, the encapsulant adheres to the adjacent surfaces of the integrated circuit and the substrate, essentially interlocking the surfaces.

摘要翻译： 提出了一种用于在集成电路周围形成网格阵列器件封装的系统和方法。 集成电路包括在下表面上的多个I / O焊盘，并且衬底的上表面包括相应的一组焊盘。 衬底还具有延伸穿过其中并且优选地基本上在该组焊盘的中心的开口（即，孔）。 形成在集成电路的I / O焊盘上的焊料凸块被放置成与该组接合焊盘的相应部件直接接触，然后被加热直到它们以C4连接方式流动。 在I / O和接合焊盘的C4连接之后，衬底和附接的集成电路位于形成在两个模具部分之间的模具腔内，并且通过衬底的开口注入液体密封剂材料，使得密封剂填充 模腔。 耦合的I / O和接合焊盘被液体密封剂包围。 液体密封剂优选为C4底部填充材料。 通过在压力下注入液体密封剂，减少了分配液体密封剂所需的时间以及存在于液体密封剂中的空隙数。 在密封剂至少部分固化之后，分离模具部分，并且去除封装的半导体器件。 当完全固化和硬化时，密封剂粘附到集成电路和基板的相邻表面，基本上使表面互锁。

公开(公告)号：US6057594A

公开(公告)日：2000-05-02

申请号：US842379

申请日：1997-04-23

申请人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

IPC分类号： H01L23/433 ,  H01L23/495 ,  H01L23/498 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/4334 ,  H01L23/49572 ,  H01L23/49816 ,  H01L2924/0002

摘要： A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.

摘要翻译： 模制的带状球栅阵列封装具有基底结构，其包括导热基底和柔性带，该柔性带从柔性带和基底之间的模制塑料材料的表面上的相对区域延伸。 柔性带具有至少一个导电金属引线图案，其可以被定位在面向基板的带的一侧，并具有多个孔，用于将导电引线图案从带的相对侧暴露以进行焊球接合。 半导体集成电路芯片通过引线将芯片上的接合焊盘互连到金属引线图案，在柔性带的相对区域之间的基板的中心部分上安装。 然后将芯片和引线接合封装在基板上。 该结构是经济的并且允许来自集成电路的高功率耗散。 在制造集成电路封装中的成型工艺是经济的，并且易于使用注塑成型。

公开(公告)号：US5841191A

公开(公告)日：1998-11-24

申请号：US837530

申请日：1997-04-21

申请人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

发明人： Chok J. Chia ,  Qwai H. Low ,  Maniam Alagaratnam

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/50 ,  H01L23/52 ,  H01L23/48

CPC分类号： H01L24/49 ,  H01L23/50 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107

摘要： A ball grid array package in which one or more conductive rings are positioned on a surface of the package substrate along with solder bond contacts on the surface of the substrate to facilitate the interconnection of wire bonds to an integrated circuit chip on the surface of the substrate. The use of rings allows for better distribution of power to the chip since a plurality of wires can be connected between the chip and the conductive rings for power distribution. The rings create a different shelf for the power and ground bonds on the substrate, and by providing a vertical separation between the surfaces of the rings and bonding pads on the surface of the substrate more bonds in the package can be accommodated.

摘要翻译： 一种球栅阵列封装，其中一个或多个导电环与衬底表面上的焊料接合位置一起定位在封装衬底的表面上，以便于引线键合到衬底表面上的集成电路芯片 。 由于可以在芯片和用于配电的导电环之间连接多根导线，所以使用环允许更好地将功率分配到芯片。 这些环形成不同的搁板，用于基板上的电源和接地键，并且通过在环的表面和衬底表面上的接合焊盘之间提供垂直间隔，可以容纳封装中更多的接合。