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1.发明授权Method and structure for eliminating aluminum terminal pad material in semiconductor devices 有权在半导体器件中消除铝端子焊盘材料的方法和结构公开(公告)号：US07375021B2
公开(公告)日：2008-05-20
申请号：US11308539
申请日：2006-04-04
IPC分类号： H01L21/44
CPC分类号： H01L24/03 , H01L23/3192 , H01L24/05 , H01L24/11 , H01L2224/03019 , H01L2224/039 , H01L2224/0401 , H01L2224/05018 , H01L2224/05083 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05558 , H01L2224/05572 , H01L2224/05647 , H01L2224/1146 , H01L2224/13022 , H01L2224/13116 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/01074 , H01L2924/00011 , H01L2924/00015 , H01L2924/01039 , H01L2224/05552
摘要： A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is deposited over the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.
摘要翻译： 用于远端（FBEOL）半导体器件形成的方法包括在半导体晶片的上层形成端子铜焊盘，在端子铜焊盘上形成绝缘堆叠，以及在端部铜焊盘的一部分内图案化和打开端子通孔 绝缘堆叠，以便留下保护端子铜焊盘的绝缘堆叠的底盖层。 在绝缘堆叠的顶部上形成并图案化有机钝化层，并且去除端子铜焊盘上的底盖层。 球限制冶金（BLM）堆叠沉积在有机钝化层和端子铜焊盘上，并且在BLM堆叠的图案化部分上形成焊球连接。
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公开(公告)号：US20090243098A1
公开(公告)日：2009-10-01
申请号：US12054713
申请日：2008-03-25
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05026 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05558 , H01L2224/05572 , H01L2224/0558 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.
摘要翻译： 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。
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公开(公告)号：US20090032974A1
公开(公告)日：2009-02-05
申请号：US11831026
申请日：2007-07-31
IPC分类号： H01L21/00 , H01L23/528
CPC分类号： H01L21/563 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/131 , H01L2224/16225 , H01L2224/26145 , H01L2224/29036 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/831 , H01L2224/83379 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/13099 , H01L2224/05599
摘要： A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.
摘要翻译： 组装微电子倒装芯片布置的方法包括将具有限定长度的芯片附接到支撑衬底，其中芯片在支撑衬底上形成具有限定长度的芯片阴影线，在外部形成第一非可湿润区域 在芯片阴影线外部的支撑基板的一部分上形成第二不可润湿区域，在芯片上填充并形成圆角，其中圆角不延伸超过芯片阴影线，以及 硬化底部填充物，包括圆角。
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公开(公告)号：US08022543B2
公开(公告)日：2011-09-20
申请号：US12054713
申请日：2008-03-25
IPC分类号： H01L23/48
CPC分类号： H01L24/11 , H01L2224/0401 , H01L2224/05018 , H01L2224/05022 , H01L2224/05026 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05181 , H01L2224/05184 , H01L2224/05558 , H01L2224/05572 , H01L2224/0558 , H01L2224/05647 , H01L2224/05655 , H01L2224/13022 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2224/05552 , H01L2924/00014 , H01L2924/013
摘要： A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball.
摘要翻译： 第一金属扩散阻挡层形成在暴露在钝化层的开口中的最后一级金属板上。 任选地，在第一金属扩散阻挡层上形成金属粘附促进层。 在金属粘合促进层上形成元素金属导电层，其提供高导电性结构，其由于材料的导电性高于或高于上述层而导致电流均匀分布。 形成第二金属扩散阻挡层和润湿促进层的叠层，其上结合有C4球。 元素金属导电层将电流均匀分布在下焊管冶金结构内，从而在C4球中引起更均匀的电流分布，提高C4球的电迁移阻力。
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公开(公告)号：US07919356B2
公开(公告)日：2011-04-05
申请号：US11831026
申请日：2007-07-31
IPC分类号： H01L21/44
CPC分类号： H01L21/563 , H01L24/32 , H01L2224/05568 , H01L2224/05573 , H01L2224/131 , H01L2224/16225 , H01L2224/26145 , H01L2224/29036 , H01L2224/321 , H01L2224/32225 , H01L2224/73204 , H01L2224/831 , H01L2224/83379 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2924/014 , H01L2224/13099 , H01L2224/05599
摘要： A method of assembling a microelectronic flip-chip arrangement includes attaching a chip having a defined length to a supporting substrate, wherein the chip forms a chip shadow line of the defined length on the supporting substrate, creating a first non-wettable zone on an outer portion of the bottom surface of the chip, creating a second non-wettable zone on a portion of the supporting substrate outside the chip shadow line, underfilling the chip and forming a fillet, wherein the fillet does not extend beyond the chip shadow line, and hardening the underfill including the fillet.
摘要翻译： 组装微电子倒装芯片布置的方法包括将具有限定长度的芯片附接到支撑衬底，其中芯片在支撑衬底上形成具有限定长度的芯片阴影线，在外部形成第一非可湿润区域 在芯片阴影线外部的支撑基板的一部分上形成第二不可润湿区域，在芯片上填充并形成圆角，其中圆角不延伸超过芯片阴影线，以及 硬化底部填充物，包括圆角。
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公开(公告)号：US20080029898A1
公开(公告)日：2008-02-07
申请号：US11461511
申请日：2006-08-01
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： Via stack structures are disclosed. In one embodiment, a structure includes a via stack including: a first substantially cross-shaped line in a first dielectric layer; a second substantially cross-shaped line set in a second dielectric layer, and a via stud coupling the first substantially cross-shaped line to the second substantially cross-shaped line. In another embodiment, a structure includes a first via stack, and a second via stack, wherein the first via stack and the second via stack extend in a divergent manner from one another. Each via stack structure is useful for support, for example, in under wire bond applications. The via stack structures can be mixed with other via stack structures and selectively placed within a layout to replace conventional metal plate and via stud array configurations.
摘要翻译： 公开了通过堆叠结构。 在一个实施例中，结构包括通孔堆叠，其包括：第一介电层中的第一基本十字形的线; 设置在第二电介质层中的第二基本上十字形的线，以及将第一基本上十字形的线耦合到第二基本十字形线的通孔柱。 在另一个实施例中，结构包括第一通孔堆叠和第二通孔堆叠，其中第一通孔堆叠和第二通孔堆叠以彼此发散的方式延伸。 每个通孔堆叠结构可用于支持，例如在引线键合应用中。 通孔堆叠结构可以与其它通孔堆叠结构混合并且选择性地放置在布局内以代替传统的金属板和经由螺柱阵列配置。
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公开(公告)号：US20080038913A1
公开(公告)日：2008-02-14
申请号：US11463642
申请日：2006-08-10
申请人： Mukta G. Farooq , Robert Hannon , Ian D. Melville , Kevin S. Petrarca , Donna S. Zupanski-Nielsen
发明人： Mukta G. Farooq , Robert Hannon , Ian D. Melville , Kevin S. Petrarca , Donna S. Zupanski-Nielsen
IPC分类号： H01L21/44
CPC分类号： H01L24/02 , H01L24/45 , H01L2224/04042 , H01L2224/45144 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2224/48
摘要： Methods of forming an aluminum-free wire bond pad and the pad so formed are disclosed. In one embodiment, the method includes forming an opening through a dielectric layer to a last metal of a chip; forming a tantalum nitride (TaN) layer over the chip and over the opening; removing the tantalum nitride (TaN) layer outside of the opening; forming a passivation mask layer over the chip including a passivation mask opening over the last metal; forming a titanium tungsten (TiW) layer and a copper (Cu) layer over the chip; forming a mask layer over the chip including a mask opening to the copper (Cu) layer over the last metal; forming a nickel (Ni) layer and a copper (Cu) layer and then a gold (Au) layer in the mask opening; and removing the mask.
摘要翻译： 公开了形成无铝线接合焊盘和如此形成的焊盘的方法。 在一个实施例中，该方法包括通过电介质层形成开口至芯片的最后一个金属; 在芯片上并在开口上形成氮化钽（TaN）层; 去除开口外面的氮化钽（TaN）层; 在所述芯片上形成钝化掩模层，其包括在最后一个金属上的钝化掩模开口; 在芯片上形成钛钨（TiW）层和铜（Cu）层; 在所述芯片上形成掩模层，所述掩模层包括在最后金属上的铜（Cu）层的掩模开口; 在掩模开口中形成镍（Ni）层和铜（Cu）层，然后形成金（Au）层; 并取下面罩。
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公开(公告)号：US08610283B2
公开(公告)日：2013-12-17
申请号：US12573183
申请日：2009-10-05
CPC分类号： H01L21/02697 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05016 , H01L2224/05026 , H01L2224/05027 , H01L2224/05124 , H01L2224/05147 , H01L2224/05157 , H01L2224/05187 , H01L2224/05562 , H01L2224/05572 , H01L2224/131 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/15787 , H01L2924/04953 , H01L2924/01014 , H01L2224/05552 , H01L2924/00
摘要： Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.
摘要翻译： 公开了一种半导体器件，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在另一实施例中，在绝缘层和铜插塞之间也可以有铝层。 还公开了制造半导体器件的方法。
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9.发明授权公开(公告)号：US07573115B2
公开(公告)日：2009-08-11
申请号：US11559130
申请日：2006-11-13
申请人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
发明人： Ian D. Melville , Mukta G. Farooq , Dae Young Jung
IPC分类号： H01L23/52
CPC分类号： H01L24/05 , H01L24/13 , H01L2224/02235 , H01L2224/02351 , H01L2224/0401 , H01L2224/05073 , H01L2224/05094 , H01L2224/05095 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13006 , H01L2224/131 , H01L2224/16 , H01L2924/00013 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01057 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05599 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.
摘要翻译： 本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。 在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。 通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。
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公开(公告)号：US20090039515A1
公开(公告)日：2009-02-12
申请号：US11836819
申请日：2007-08-10
CPC分类号： H01L23/5329 , H01L23/556 , H01L2924/0002 , Y10S438/958 , Y10S438/967 , H01L2924/00
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。
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