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1.发明授权Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die 有权具有嵌入式半导体芯片的预制散热器框架的半导体装置和方法公开(公告)号：US08518749B2
公开(公告)日：2013-08-27
申请号：US12489177
申请日：2009-06-22
CPC分类号： H01L23/562 , H01L21/4871 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L21/78 , H01L23/3114 , H01L23/3128 , H01L23/34 , H01L23/3672 , H01L23/4334 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/95 , H01L2224/0401 , H01L2224/04105 , H01L2224/1134 , H01L2224/13022 , H01L2224/16 , H01L2224/16235 , H01L2224/20 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.
摘要翻译： 通过将预制散热器框架安装在临时衬底上来制造半导体器件。 散热器框架包括平板上的垂直体。 将半导体管芯安装到散热器框架上用于散热。 在垂直体和半导体管芯周围沉积密封剂，同时留下露出的半导体管芯上的接触焊盘。 可以使用晶片级直接/顶栅模制工艺或晶片级膜辅助模制工艺来沉积密封剂。 在半导体管芯上形成互连结构。 互连结构包括形成在半导体管芯上的第一导电层，形成在第一导电层上的绝缘层，以及形成在第一导电层和绝缘层上的第二导电层。 去除临时衬底，将切割带施加到散热器框架，并且半导体管芯被切割。
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公开(公告)号：US08241954B2
公开(公告)日：2012-08-14
申请号：US11949133
申请日：2007-12-03
IPC分类号： H01L21/00
CPC分类号： H01L23/5389 , H01L23/3114 , H01L24/18 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/24145 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48464 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2225/06506 , H01L2225/06524 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/30105 , H01L2224/83 , H01L2224/82 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a wafer level chip scale package (WLCSP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLCSP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.
摘要翻译： 在晶片级芯片级封装（WLCSP）中，半导体管芯具有在其有源表面上形成的有源电路和接触焊盘。 第二半导体管芯设置在第一半导体管芯上。 第一再分配层（RDL）电连接第一和第二半导体管芯。 第三半导体管芯设置在第二半导体管芯上。 第二和第三半导体管芯用粘合剂附着。 第二RDL电连接第一，第二和第三半导体管芯。 第二个RDL可以是接合线。 钝化层隔离RDL和第二和第三半导体管芯。 在WLCSP的表面上形成多个焊料凸块。 焊料凸块形成在电连接到RDL上的凸起下金属化处。 焊料凸块通过第一和第二RDL电连接到第一，第二或第三半导体管芯。
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公开(公告)号：US09142514B2
公开(公告)日：2015-09-22
申请号：US13546726
申请日：2012-07-11
IPC分类号： H01L21/00 , H01L23/538 , H01L23/00 , H01L25/065 , H01L25/00 , H01L23/31
CPC分类号： H01L23/5389 , H01L23/3114 , H01L24/18 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/24145 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48464 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2225/06506 , H01L2225/06524 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/30105 , H01L2224/83 , H01L2224/82 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a wafer level chip scale package (WLCSP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLCSP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.
摘要翻译： 在晶片级芯片级封装（WLCSP）中，半导体管芯具有在其有源表面上形成的有源电路和接触焊盘。 第二半导体管芯设置在第一半导体管芯上。 第一再分配层（RDL）电连接第一和第二半导体管芯。 第三半导体管芯设置在第二半导体管芯上。 第二和第三半导体管芯用粘合剂附着。 第二RDL电连接第一，第二和第三半导体管芯。 第二个RDL可以是接合线。 钝化层隔离RDL和第二和第三半导体管芯。 在WLCSP的表面上形成多个焊料凸块。 焊料凸块形成在电连接到RDL上的凸起下金属化处。 焊料凸块通过第一和第二RDL电连接到第一，第二或第三半导体管芯。
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公开(公告)号：US20120276691A1
公开(公告)日：2012-11-01
申请号：US13546726
申请日：2012-07-11
IPC分类号： H01L21/60
CPC分类号： H01L23/5389 , H01L23/3114 , H01L24/18 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/24145 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48464 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2225/06506 , H01L2225/06524 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/30105 , H01L2224/83 , H01L2224/82 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a wafer level chip scale package (WLSCP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLSCP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.
摘要翻译： 在晶片级芯片级封装（WLSCP）中，半导体管芯具有在其有源表面上形成的有源电路和接触焊盘。 第二半导体管芯设置在第一半导体管芯上。 第一再分配层（RDL）电连接第一和第二半导体管芯。 第三半导体管芯设置在第二半导体管芯上。 第二和第三半导体管芯用粘合剂附着。 第二RDL电连接第一，第二和第三半导体管芯。 第二个RDL可以是接合线。 钝化层隔离RDL和第二和第三半导体管芯。 在WLSCP的表面上形成多个焊料凸块。 焊料凸块形成在电连接到RDL上的凸起下金属化处。 焊料凸块通过第一和第二RDL电连接到第一，第二或第三半导体管芯。
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5.发明申请Semiconductor Device and Method of Forming Prefabricated Heat Spreader Frame with Embedded Semiconductor Die 有权半导体器件及嵌入式半导体模具预制散热器框架的制作方法公开(公告)号：US20100320588A1
公开(公告)日：2010-12-23
申请号：US12489177
申请日：2009-06-22
IPC分类号： H01L23/48 , H01L21/768 , H01L23/36
CPC分类号： H01L23/562 , H01L21/4871 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L21/78 , H01L23/3114 , H01L23/3128 , H01L23/34 , H01L23/3672 , H01L23/4334 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/95 , H01L2224/0401 , H01L2224/04105 , H01L2224/1134 , H01L2224/13022 , H01L2224/16 , H01L2224/16235 , H01L2224/20 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.
摘要翻译： 通过将预制散热器框架安装在临时衬底上来制造半导体器件。 散热器框架包括平板上的垂直体。 将半导体管芯安装到散热器框架上用于散热。 在垂直体和半导体管芯周围沉积密封剂，同时留下露出的半导体管芯上的接触焊盘。 可以使用晶片级直接/顶栅模制工艺或晶片级膜辅助模制工艺来沉积密封剂。 在半导体管芯上形成互连结构。 互连结构包括形成在半导体管芯上的第一导电层，形成在第一导电层上的绝缘层，以及形成在第一导电层和绝缘层上的第二导电层。 去除临时衬底，将切割带施加到散热器框架，并且半导体管芯被切割。
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公开(公告)号：US20090140441A1
公开(公告)日：2009-06-04
申请号：US11949133
申请日：2007-12-03
IPC分类号： H01L23/538 , H01L21/00
CPC分类号： H01L23/5389 , H01L23/3114 , H01L24/18 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/18 , H01L2224/24145 , H01L2224/24146 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48464 , H01L2224/73265 , H01L2224/73267 , H01L2224/94 , H01L2225/06506 , H01L2225/06524 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15184 , H01L2924/15311 , H01L2924/30105 , H01L2224/83 , H01L2224/82 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In a wafer level chip scale package (WLSCP), a semiconductor die has active circuits and contact pads formed on its active surface. A second semiconductor die is disposed over the first semiconductor die. A first redistribution layer (RDL) electrically connects the first and second semiconductor die. A third semiconductor die is disposed over the second semiconductor die. The second and third semiconductor die are attached with an adhesive. A second RDL electrically connects the first, second, and third semiconductor die. The second RDL can be a bond wire. Passivation layers isolate the RDLs and second and third semiconductor die. A plurality of solder bumps is formed on a surface of the WLSCP. The solder bumps are formed on under bump metallization which electrically connects to the RDLs. The solder bumps electrically connect to the first, second, or third semiconductor die through the first and second RDLs.
摘要翻译： 在晶片级芯片级封装（WLSCP）中，半导体管芯具有在其有源表面上形成的有源电路和接触焊盘。 第二半导体管芯设置在第一半导体管芯上。 第一再分配层（RDL）电连接第一和第二半导体管芯。 第三半导体管芯设置在第二半导体管芯上。 第二和第三半导体管芯用粘合剂附着。 第二RDL电连接第一，第二和第三半导体管芯。 第二个RDL可以是接合线。 钝化层隔离RDL和第二和第三半导体管芯。 在WLSCP的表面上形成多个焊料凸点。 焊料凸块形成在电连接到RDL上的凸起下金属化处。 焊料凸块通过第一和第二RDL电连接到第一，第二或第三半导体管芯。
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7.发明授权Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps 有权半导体器件和用导电凸块互连的具有内部已知的良好裸芯片的PiP的形成方法公开(公告)号：US08283209B2
公开(公告)日：2012-10-09
申请号：US12635631
申请日：2009-12-10
IPC分类号： H01L21/00
CPC分类号： H01L23/49548 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/49541 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16225 , H01L2224/24226 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/83411 , H01L2224/83424 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/85001 , H01L2225/0651 , H01L2225/06524 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15747 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/0105 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
摘要翻译： PiP半导体器件具有内部已知的良好半导体封装。 在半导体封装中，在临时载体中形成第一通孔。 第一导电层形成在载体上并进入第一通孔中。 第一通孔中的第一导电层形成导电凸块。 第一半导体管芯安装到第一导电层。 第一密封剂沉积在第一模具和载体上。 半导体封装被安装到基板上。 第二半导体管芯安装到与第一管芯相对的第一导电层。 第二密封剂沉积在第二管芯和半导体封装上。 在第二密封剂中形成第二通孔以暴露导电凸块。 第二导电层形成在第二密封剂上并进入第二通孔中。 第二导电层电连接到第二管芯。
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8.发明授权Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps 有权半导体器件和用导电凸块互连的具有内部已知的良好管芯的PIP形成方法公开(公告)号：US08884418B2
公开(公告)日：2014-11-11
申请号：US13606451
申请日：2012-09-07
IPC分类号： H01L23/24 , H01L23/28 , H01L23/48 , H01L25/11 , H01L23/31 , H01L23/538 , H01L21/56 , H01L21/683 , H01L23/498 , H01L23/00 , H01L25/065 , H01L25/00 , H01L23/495
CPC分类号： H01L23/49548 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/49541 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16225 , H01L2224/24226 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/83411 , H01L2224/83424 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/85001 , H01L2225/0651 , H01L2225/06524 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15747 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/0105 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
摘要翻译： PiP半导体器件具有内部已知的良好半导体封装。 在半导体封装中，在临时载体中形成第一通孔。 第一导电层形成在载体上并进入第一通孔中。 第一通孔中的第一导电层形成导电凸块。 第一半导体管芯安装到第一导电层。 第一密封剂沉积在第一模具和载体上。 半导体封装被安装到基板上。 第二半导体管芯安装到与第一管芯相对的第一导电层。 第二密封剂沉积在第二管芯和半导体封装上。 在第二密封剂中形成第二通孔以暴露导电凸块。 第二导电层形成在第二密封剂上并进入第二通孔中。 第二导电层电连接到第二管芯。
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9.发明申请SEMICONDUCTOR DEVICE AND METHOD OF FORMING PIP WITH INNER KNOWN GOOD DIE INTERCONNECTED WITH CONDUCTIVE BUMPS 有权半导体器件和形成具有与导电性气体相互连接的内部良好芯片的管道的方法公开(公告)号：US20140284788A9
公开(公告)日：2014-09-25
申请号：US13606451
申请日：2012-09-07
IPC分类号： H01L23/485
CPC分类号： H01L23/49548 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/49541 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16225 , H01L2224/24226 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/83411 , H01L2224/83424 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/85001 , H01L2225/0651 , H01L2225/06524 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15747 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/0105 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
摘要翻译： PiP半导体器件具有内部已知的良好半导体封装。 在半导体封装中，在临时载体中形成第一通孔。 第一导电层形成在载体上并进入第一通孔中。 第一通孔中的第一导电层形成导电凸块。 第一半导体管芯安装到第一导电层。 第一密封剂沉积在第一模具和载体上。 半导体封装被安装到基板上。 第二半导体管芯安装到与第一管芯相对的第一导电层。 第二密封剂沉积在第二管芯和半导体封装上。 在第二密封剂中形成第二通孔以暴露导电凸块。 第二导电层形成在第二密封剂上并进入第二通孔中。 第二导电层电连接到第二管芯。
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10.发明申请Semiconductor Device and Method of Forming PIP with Inner Known Good Die Interconnected with Conductive Bumps 有权半导体器件和形成具有内部已知良好导体的PIP与导电凸块相互连接的方法公开(公告)号：US20110140263A1
公开(公告)日：2011-06-16
申请号：US12635631
申请日：2009-12-10
CPC分类号： H01L23/49548 , H01L21/4832 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/3135 , H01L23/49541 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16 , H01L2224/16225 , H01L2224/24226 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29299 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/83411 , H01L2224/83424 , H01L2224/83439 , H01L2224/83444 , H01L2224/83447 , H01L2224/83455 , H01L2224/85001 , H01L2225/0651 , H01L2225/06524 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15747 , H01L2924/16195 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/3025 , H01L2924/00 , H01L2924/0105 , H01L2924/0665 , H01L2224/29099 , H01L2224/29199 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
摘要翻译： PiP半导体器件具有内部已知的良好半导体封装。 在半导体封装中，在临时载体中形成第一通孔。 第一导电层形成在载体上并进入第一通孔中。 第一通孔中的第一导电层形成导电凸块。 第一半导体管芯安装到第一导电层。 第一密封剂沉积在第一模具和载体上。 半导体封装被安装到基板上。 第二半导体管芯安装到与第一管芯相对的第一导电层。 第二密封剂沉积在第二管芯和半导体封装上。 在第二密封剂中形成第二通孔以暴露导电凸块。 第二导电层形成在第二密封剂上并进入第二通孔中。 第二导电层电连接到第二管芯。
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