公开(公告)号：US20120018885A1

公开(公告)日：2012-01-26

申请号：US12960843

申请日：2010-12-06

申请人： Go Eun Lee ,  Taeje Cho ,  Un-Byoung Kang ,  Seongmin Ryu ,  Jung-Hwan Kim ,  Tae Hong Min

发明人： Go Eun Lee ,  Taeje Cho ,  Un-Byoung Kang ,  Seongmin Ryu ,  Jung-Hwan Kim ,  Tae Hong Min

IPC分类号： H01L23/498

CPC分类号： H01L23/481 ,  H01L23/49816 ,  H01L23/49855 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.

摘要翻译： 半导体装置包括基底基板和布置在基底基板上的逻辑芯片。 逻辑芯片包括存储器控制电路，第一通孔硅通孔和第二硅通孔。 存储器控制电路设置在逻辑芯片的基板的第一表面上，并且存储芯片设置在逻辑芯片的基板的第二表面上。 第一通孔硅通过电连接存储器控制电路和存储器芯片，第二通孔硅通孔电连接到存储器芯片，并被配置为向存储器芯片发送功率，第二通孔硅通孔与逻辑电绝缘 芯片，并且逻辑芯片的基板的第一表面面向基底。

公开(公告)号：US08884416B2

公开(公告)日：2014-11-11

申请号：US12960843

申请日：2010-12-06

申请人： Go Eun Lee ,  Taeje Cho ,  Un-Byoung Kang ,  Seongmin Ryu ,  Jung-Hwan Kim ,  Tae Hong Min

发明人： Go Eun Lee ,  Taeje Cho ,  Un-Byoung Kang ,  Seongmin Ryu ,  Jung-Hwan Kim ,  Tae Hong Min

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/481 ,  H01L23/49816 ,  H01L23/49855 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.

摘要翻译： 半导体装置包括基底基板和布置在基底基板上的逻辑芯片。 逻辑芯片包括存储器控制电路，第一通孔硅通孔和第二硅通孔。 存储器控制电路设置在逻辑芯片的基板的第一表面上，并且存储芯片设置在逻辑芯片的基板的第二表面上。 第一通孔硅通过电连接存储器控制电路和存储器芯片，第二通孔硅通孔电连接到存储器芯片，并被配置为向存储器芯片发送功率，第二通孔硅通孔与逻辑电绝缘 芯片，并且逻辑芯片的基板的第一表面面向基底。

公开(公告)号：US20120156823A1

公开(公告)日：2012-06-21

申请号：US13281870

申请日：2011-10-26

申请人： Jong-Yun MYUNG ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

发明人： Jong-Yun MYUNG ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

IPC分类号： H01L31/18 ,  H01L21/50 ,  H01L21/78

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

摘要翻译： 一种形成半导体器件的方法包括制备其上形成有多个芯片的半导体衬底和设置在芯片之间的划线，同时形成在划线中具有第一深度的凹槽，以及穿透芯片的通孔，并具有 第二个深度。 芯片沿凹槽分开。 第一深度小于第二深度。

公开(公告)号：US08890325B2

公开(公告)日：2014-11-18

申请号：US13244544

申请日：2011-09-25

申请人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min

发明人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min

IPC分类号： H01L23/48 ,  H01L33/48 ,  H01L33/62 ,  H01L33/00

CPC分类号： H01L33/486 ,  H01L33/0079 ,  H01L33/62 ,  H01L2224/16 ,  H01L2933/0066

摘要： In one embodiment, a heterojunction structure includes a first substrate; a second substrate comprising an electrode pad, the second substrate joined to the first substrate by an adhesive layer interposed between the first and second substrates, the first substrate and the adhesive layer having a via hole penetrating therethrough to expose a region of the electrode pad; a connection electrode disposed in the via hole and contacting the electrode pad; and an insulation layer electrically insulating the connection electrode from the first substrate. One of the first and second substrates has a thermal expansion coefficient different than a thermal expansion coefficient of the other of the first and second substrates, and at least one of the adhesive layer or the insulation layer comprises an organic material.

摘要翻译： 在一个实施例中，异质结结构包括第一衬底; 第二基板，其包括电极焊盘，所述第二基板通过插入在所述第一和第二基板之间的粘合剂层连接到所述第一基板，所述第一基板和所述粘合剂层具有贯穿其中的通孔，以暴露所述电极焊盘的区域; 连接电极，设置在所述通孔中并与所述电极焊盘接触; 以及将连接电极与第一基板电绝缘的绝缘层。 第一和第二基板中的一个具有不同于第一和第二基板中的另一个的热膨胀系数的热膨胀系数，并且粘合剂层或绝缘层中的至少一个包括有机材料。

公开(公告)号：US08450856B2

公开(公告)日：2013-05-28

申请号：US13240533

申请日：2011-09-22

申请人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

发明人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC分类号： H01L23/48

CPC分类号： H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

公开(公告)号：US20120153498A1

公开(公告)日：2012-06-21

申请号：US13240533

申请日：2011-09-22

申请人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

发明人： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC分类号： H01L23/48

CPC分类号： H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

摘要翻译： 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。 有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。 由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。 此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。 这也减少了分层问题。 此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。 因此，可以实现具有增强的可靠性的半导体器件。

公开(公告)号：US08563349B2

公开(公告)日：2013-10-22

申请号：US13281870

申请日：2011-10-26

申请人： Jong-Yun Myung ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

发明人： Jong-Yun Myung ,  Hyuek-Jae Lee ,  Ji-Sun Hong ,  Tae-Je Cho ,  Un-Byoung Kang ,  Hyung-Sun Jang ,  Eun-Mi Kim ,  Jung-Hwan Kim ,  Tae-Hong Min

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/1464 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12043 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.

摘要翻译： 一种形成半导体器件的方法包括制备其上形成有多个芯片的半导体衬底和设置在芯片之间的划线，同时形成在划线中具有第一深度的凹槽，以及穿透芯片的通孔，并具有 第二个深度。 芯片沿凹槽分开。 第一深度小于第二深度。

公开(公告)号：US08558371B2

公开(公告)日：2013-10-15

申请号：US13011286

申请日：2011-01-21

申请人： JiSun Hong ,  Taeje Cho ,  Un-Byoung Kang ,  Hyuekjae Lee ,  Youngbok Kim ,  Hyung-sun Jang

发明人： JiSun Hong ,  Taeje Cho ,  Un-Byoung Kang ,  Hyuekjae Lee ,  Youngbok Kim ,  Hyung-sun Jang

IPC分类号： H01L23/12

CPC分类号： H01L23/3114 ,  H01L21/50 ,  H01L21/76898 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer.

摘要翻译： 提供了一种晶片级封装方法和使用其制造的半导体器件。 在该方法中，提供包括多个芯片的基板。 在对应于多个芯片的边界的基板上形成粘合剂层。 覆盖基板的上部并且具有至少一个露出多个芯片之间的边界处的粘合剂层或基板的开口的盖板附接到粘合剂层。

公开(公告)号：US20170004990A1

公开(公告)日：2017-01-05

申请号：US15112429

申请日：2014-03-19

申请人： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

发明人： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

IPC分类号： H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L21/6836 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5446 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/304 ,  H01L2221/68363 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/03 ,  H01L2224/85

摘要： Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.

摘要翻译： 提供制造半导体器件的方法。 根据该方法，第一胶合层，第一剥离层，第二胶层和第二剥离层可以顺序插入载体和器件晶片之间。 所有第一胶合层，第一释放层，第二胶层和第二剥离层可以由热固性树脂形成。

公开(公告)号：US10157766B2

公开(公告)日：2018-12-18

申请号：US15112429

申请日：2014-03-19

申请人： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

发明人： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

IPC分类号： H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

摘要： Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.