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公开(公告)号：US11972970B1
公开(公告)日：2024-04-30
申请号：US17361186
申请日：2021-06-28
发明人： Florian G. Herrault , Joel Wong
IPC分类号： H01L21/683 , H01L21/768 , H01L21/82 , H01L21/8234
CPC分类号： H01L21/6836 , H01L21/76802 , H01L21/8213 , H01L21/8234
摘要： An array of III-V material transistors singulated from a Si or SiC wafer disposed on a stretchable tape compatible with pick and place tools and a method of forming same.
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公开(公告)号：US10829386B1
公开(公告)日：2020-11-10
申请号：US16203788
申请日：2018-11-29
发明人： Adam F. Gross , Xin N. Guan , Shanying Cui , Florian G. Herrault
摘要： Some variations provide a method of making water-dispersed hexaferrite nanoparticles, comprising: providing a first salt containing iron, a second salt containing barium and/or strontium, and a third salt containing an anion or cation that is capable of forming a ligand with the hexaferrite nanoparticles; combining the first salt, second salt, third salt, and water to form a reaction mixture; subjecting the reaction mixture to effective reaction conditions to produce hexaferrite nanoparticles with the anion or cation in the third salt forming a ligand on the surface, so that the hexaferrite nanoparticles are dissolved and/or suspended in the reaction mixture; and obtaining water-dispersed hexaferrite nanoparticles with an average zeta potential of at least ±20 mV. The water-dispersed hexaferrite nanoparticles have a hexaferrite content of at least 85 wt %. The method may further include assembling water-dispersed hexaferrite nanoparticles into a magnetic component, such as a self-biased hexaferrite film on a semiconductor substrate.
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公开(公告)号：US10026672B1
公开(公告)日：2018-07-17
申请号：US15299348
申请日：2016-10-20
IPC分类号： H01L21/00 , H01L29/06 , H01L23/367 , H01L21/48 , H01L23/373
摘要： A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management. After die embedding, wafer-level front side interconnects are fabricated to interconnect the various chips and with each other. The wafer is then diced into individual metal-embedded chip assembly (MECA) modules, and forms the level one for multi-scale R-MECA integration. These modules are subsequently integrated into another wafer or board using the same integration approach recursively. Additional components such as discrete passive resistors, capacitors and inductors can be integrated at the second level, once the high-resolution, high-density integration has been performed at level zero. This recursive integration offers a practical solution to build very large scale integrated systems and subsystems.
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公开(公告)号：US11536800B2
公开(公告)日：2022-12-27
申请号：US17207470
申请日：2021-03-19
IPC分类号： H01L23/538 , H01L23/482 , H01L23/367 , H01L25/065 , H01L25/16 , H01L21/56 , H01L21/683 , G01S7/03 , H01Q1/32 , H01Q23/00
摘要： An integrated radar circuit comprising: a first substrate, of a first semiconductor material, said first substrate comprising an integrated transmit and receive radar circuit; a second substrate, of a second semiconductor material, said second substrate comprising at least on through-substrate cavity having cavity walls; at least one discrete transistor chip, of a third semiconductor material, said at least one discrete transistor chip having chip walls and being held in said at least one through-substrate cavity by a metal filling extending from at least one cavity wall to at least one chip wall; a conductor on said second substrate, electrically connecting a portion of said integrated transmit and receive radar circuit to a discrete transistor on said at least one discrete transistor chip.
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公开(公告)号：US10950562B1
公开(公告)日：2021-03-16
申请号：US16559486
申请日：2019-09-03
IPC分类号： H01L23/66 , H01L23/367 , H01L23/04 , H01L21/48 , H01L21/768 , H01L21/288 , H01L21/52
摘要： A microwave electronic component comprising a substrate having top and bottom substrate surfaces; the substrate comprising an aperture between the top and bottom substrate surfaces; a metallic heat sink filling the aperture; a microwave integrated circuit having a top circuit surface with at least one microwave signal port and a bottom circuit surface in contact with the metallic heat sink; a signal line comprising at least a metallic via between the top and bottom substrate surfaces, and a top signal conductor arranged between the microwave signal port and the metallic via; wherein the dimensions and location of the metallic via are chosen such that the metallic via forms, together with the metallic heat sink, a first impedance-matched non-coaxial transmission line.
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公开(公告)号：US20200006833A1
公开(公告)日：2020-01-02
申请号：US16396074
申请日：2019-04-26
摘要： An RF circulator in combination with a RF integrated circuit, the RF integrated circuit having a plurality of RF waveguide or waveguide-like structures in or on the RF integrated circuit, the RF circulator comprising a disk of ferrite material disposed on a metallic material disposed on or in the RF integrated circuit, the disk of ferrite material extending away from the RF integrated circuit when disposed thereon, the metallic portion having a plurality of apertures therein adjacent the disk of ferrite material which, in use, are in electromagnetic communication with the disk of ferrite material and with the plurality of RF waveguide or waveguide-like structures, the disk of ferrite material being disposed in a metallic cavity.
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公开(公告)号：US10388454B1
公开(公告)日：2019-08-20
申请号：US16020944
申请日：2018-06-27
摘要： A microfabricated laminated conductor, comprising at least two flat metallic conductors held together parallel by their edges by a first dielectric material anchor, such that there exists a gap of between several nanometers and several micrometers between most of the at least two flat metallic conductors.
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8.发明授权Direct IC-to-package wafer level packaging with integrated thermal heat spreaders 有权直接IC封装晶圆级封装，集成热散热器公开(公告)号：US09508652B1
公开(公告)日：2016-11-29
申请号：US14950667
申请日：2015-11-24
IPC分类号： H01L23/34 , H01L23/538 , H01L21/78 , H01L23/367 , H01L23/00 , H01L23/40
CPC分类号： H01L23/5389 , H01L21/78 , H01L23/04 , H01L23/10 , H01L23/367 , H01L23/3677 , H01L23/40 , H01L23/66 , H01L24/11 , H01L24/16 , H01L24/94 , H01L24/97 , H01L2223/6627 , H01L2223/6644 , H01L2223/6683 , H01L2224/1146 , H01L2224/13082 , H01L2224/13144 , H01L2224/16227 , H01L2224/73253 , H01L2224/81075 , H01L2224/8113 , H01L2224/81132 , H01L2224/81204 , H01L2224/81805 , H01L2224/92225 , H01L2224/94 , H01L2224/97 , H01L2924/10272 , H01L2924/1033 , H01L2924/1305 , H01L2924/1306 , H01L2924/13064 , H01L2924/14 , H01L2924/1423 , H01L2924/15 , H01L2924/15159 , H01L2924/15313 , H01L2924/157 , H01L2924/15788 , H01L2224/81 , H01L2224/83
摘要： A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height.
摘要翻译： 一种用于晶片级封装的方法包括形成一个或多个管芯，在每个管芯上形成镀金属环（PMR），形成覆盖晶片（CW），CW具有一个或多个电镀密封环，形成体晶片（BW） BW在BW的第一侧具有空腔和金属层，将相应的管芯与CW对准，使得相应管芯上的PMR与CW上的相应的电镀密封环（PSR）对准，将PMR 在相应的芯片上相应的PSR，将BW与CW对准，使得BW的相应空腔围绕结合到CW的每个相应的芯片，并且使得BW上的金属层与CW上的至少一个PSR对准 并且将BW的第一侧上的金属层与CW上的PSR接合。 每个PMR具有第一高度，并且每个PSR具有第二高度。
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9.发明授权Wafer-level die to package and die to die interconnects suspended over integrated heat sinks 有权晶圆级芯片封装和裸芯片连接在一起散布在散热片上公开(公告)号：US09385083B1
公开(公告)日：2016-07-05
申请号：US14720619
申请日：2015-05-22
IPC分类号： H01L21/00 , H01L23/10 , H01L23/528 , H01L23/36 , H01L21/768 , H01L23/532 , H05K7/20
CPC分类号： H01L24/70 , H01L21/0273 , H01L21/2885 , H01L21/568 , H01L21/6835 , H01L23/147 , H01L23/367 , H01L23/3675 , H01L23/3736 , H01L23/49822 , H01L23/5389 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/64 , H01L24/82 , H01L24/89 , H01L24/96 , H01L25/105 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/13023 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/16227 , H01L2224/24137 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/01022 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/05432 , H01L2924/06 , H01L2924/10253 , H01L2924/10271 , H01L2924/1033 , H01L2924/10335 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H05K7/20154
摘要： An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.
摘要翻译： 用于电耦合形成在相邻芯片上或邻近芯片的封装材料上的焊盘的互连，其中导电散热器设置在焊盘之间，所述互连件包括设置在两个相邻焊盘之间的金属膜层，并且设置或桥接在导电 散热器，以避免与导电散热器电接触。 电镀金属层设置在金属膜层上。 互连的制造允许使用与互连的晶片级制造兼容的制造技术来并行形成多个互连。 互连优选地遵循平滑曲线以电连接相邻的焊盘，并且遵循那些平滑的曲线，它们以可预测的方式在介于中间的导电散热器材料之间桥接。
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公开(公告)号：US11756783B1
公开(公告)日：2023-09-12
申请号：US17345932
申请日：2021-06-11
发明人： Eric Prophet , Joel Wong , Florian G. Herrault
IPC分类号： H01L21/02 , H01L21/268 , B23K26/40 , B23K101/40
CPC分类号： H01L21/02035 , B23K26/40 , H01L21/02013 , H01L21/02016 , H01L21/268 , B23K2101/40
摘要： A method for creating at least one cavity in a semiconductor substrate including the steps of:
(a) partially ablating the semiconductor substrate from the top side with a laser to form a trench in the semiconductor substrate surrounding a cross section of the semiconductor material having the desired shape,
(b) machining the backside of the semiconductor substrate partially ablated in step (a) to reduce the semiconductor substrate to a final thickness that is equal to or less than the laser ablation depth to form a plug of semiconductor material unattached to a remainder of the semiconductor substrate; and
(c) removing the plug of semiconductor material from the semiconductor substrate to form the at least one cavity with cross section of desired shape extending through the semiconductor substrate.
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