公开(公告)号：US09337124B1

公开(公告)日：2016-05-10

申请号：US14532761

申请日：2014-11-04

申请人： HRL LABORATORIES LLC

发明人： Florian G. Herrault ,  Alexandros Margomenos ,  Miroslav Micovic ,  Melanie S. Yajima ,  Eric M. Prophet

IPC分类号： H01L21/00 ,  H01L23/373 ,  H01L23/40 ,  H01L21/48 ,  H01L23/00 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/768

CPC分类号： H01L23/3736 ,  H01L23/373 ,  H01L23/3732 ,  H01L24/83 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20105 ,  H01L2924/2064

摘要： A method for forming a wafer level heat spreader includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the openings, bonding the mesh wafer to a backside of an integrated circuit (IC) wafer, the IC wafer comprising a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto to the backside of the IC wafer.

摘要翻译： 一种形成晶片级散热器的方法，包括：提供网眼晶片，所述网眼晶片在所述开口之间具有多个开口和网格区域，将所述网状晶片接合到集成电路（IC）晶片的背面，所述IC晶片包括 多个电路; 以及通过所述多个开口电镀散热材料并且到达所述IC晶片的背面。

公开(公告)号：US09276529B1

公开(公告)日：2016-03-01

申请号：US14506070

申请日：2014-10-03

申请人： HRL Laboratories, LLC

发明人： David F. Brown ,  Miroslav Micovic ,  Ara K. Kurdoghlian ,  Alexandros Margomenos

IPC分类号： H03F3/45 ,  H03F1/48 ,  H03F3/193 ,  H03F3/68

CPC分类号： H03F3/45179 ,  H03F3/193 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/408 ,  H03F2200/451 ,  H03F2203/45051 ,  H03F2203/45394 ,  H03F2203/45512 ,  H03F2203/45528 ,  H03F2203/45644 ,  H03F2203/45648 ,  H03F2203/45652

摘要： An operational amplifier includes three transconductance stages (TSs) each having a differential input and a differential output, a first and second resistor coupled between the differential output of the first TS and the differential input of the first TS, a third and fourth resistor coupled between the differential output of the third TS and the differential input of the first TS, a first and second capacitor coupled between the differential output of the third TS and the differential input of the third TS, wherein the first, second, and third TSs each include a differential input amplifier coupled to the differential input of the respective TS, a differential output amplifier coupled to the differential output of the respective TS, and a plurality of Schottky diodes coupled between the differential input amplifier and the differential output amplifier for voltage level shifting.

摘要翻译： 运算放大器包括三个跨导级（TS），每个跨导级具有差分输入和差分输出;耦合在第一TS的差分输出和第一TS的差分输入之间的第一和第二电阻，耦合在第一TS的差分输出之间的第三和第四电阻 第三TS的差分输出和第一TS的差分输入，耦合在第三TS的差分输出与第三TS的差分输入之间的第一和第二电容器，其中第一，第二和第三TS各自包括 耦合到相应TS的差分输入的差分输入放大器，耦合到相应TS的差分输出的差分输出放大器以及耦合在差分输入放大器和用于电压电平转换的差分输出放大器之间的多个肖特基二极管。

公开(公告)号：US09837372B1

公开(公告)日：2017-12-05

申请号：US15169591

申请日：2016-05-31

申请人： HRL LABORATORIES LLC

发明人： Florian G. Herrault ,  Melanie S. Yajima ,  Alexandros Margomenos ,  Miroslav Micovic

IPC分类号： H01L23/10 ,  H01L21/00 ,  H05K7/20 ,  H01L23/00 ,  H01L23/367 ,  H01L21/288 ,  H01L21/027 ,  H01L21/683 ,  H01L25/00 ,  H01L25/18 ,  H01L25/16 ,  H01L23/373

CPC分类号： H01L24/70 ,  H01L21/0273 ,  H01L21/2885 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/64 ,  H01L24/82 ,  H01L24/89 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01022 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05432 ,  H01L2924/06 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/20154

摘要： An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

公开(公告)号：US09093394B1

公开(公告)日：2015-07-28

申请号：US14107943

申请日：2013-12-16

申请人： HRL Laboratories, LLC

发明人： Alexandros Margomenos ,  Keisuke Shinohara ,  Dean C. Regan ,  Miroslav Micovic ,  Colleen M. Butler

IPC分类号： H01L21/44 ,  H01L23/31 ,  H01L21/56 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/778 ,  H01L23/5222 ,  H01L23/53295 ,  H01L24/05 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/2003 ,  H01L2224/03002 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/13064 ,  H01L2924/14

摘要： A semiconductor device comprises one or more transistors and two or more layers of dielectric material encapsulating a front side of said one or more transistors. The gate of each of said one or more transistors is located within a cavity, or air-box, in at least one of the dielectric layers, so that the gate terminal is physically separated from said dielectric material. Such an arrangement may reduce parasitic capacitance. In another arrangement, a semiconductor device comprises one or more gallium nitride high electron mobility transistors and one or more dielectric layers encapsulating a front side of said one or more transistors, wherein the gate terminal of each of said one or more transistors is located within a cavity in at least one of the one or more dielectric layers, separated from said dielectric material.

摘要翻译： 半导体器件包括一个或多个晶体管和封装所述一个或多个晶体管的前侧的两层或多层介电材料。 所述一个或多个晶体管中的每一个的栅极位于至少一个电介质层中的空腔或空气箱内，使得栅极端子与所述电介质材料物理分离。 这种布置可以减小寄生电容。 在另一种布置中，半导体器件包括一个或多个氮化镓高电子迁移率晶体管和封装所述一个或多个晶体管的前侧的一个或多个电介质层，其中所述一个或多个晶体管中的每一个的栅极端子位于 所述一个或多个电介质层中的至少一个与所述电介质材料分离。

公开(公告)号：US10217648B1

公开(公告)日：2019-02-26

申请号：US15610553

申请日：2017-05-31

申请人： HRL Laboratories, LLC

发明人： David F. Brown ,  Keisuke Shinohara ,  Miroslav Micovic ,  Alexandros Margomenos ,  Andrea Corrion ,  Hector L. Bracamontes ,  Ivan Alvarado-Rodriguez

IPC分类号： H01L21/00 ,  H01L21/48 ,  H01L23/373 ,  H01L23/46

摘要： Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.

公开(公告)号：US09508652B1

公开(公告)日：2016-11-29

申请号：US14950667

申请日：2015-11-24

申请人： HRL Laboratories, LLC

发明人： Florian G. Herrault ,  Melanie S. Yajima ,  Alexandros Margomenos

IPC分类号： H01L23/34 ,  H01L23/538 ,  H01L21/78 ,  H01L23/367 ,  H01L23/00 ,  H01L23/40

CPC分类号： H01L23/5389 ,  H01L21/78 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/40 ,  H01L23/66 ,  H01L24/11 ,  H01L24/16 ,  H01L24/94 ,  H01L24/97 ,  H01L2223/6627 ,  H01L2223/6644 ,  H01L2223/6683 ,  H01L2224/1146 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2224/81075 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81204 ,  H01L2224/81805 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15 ,  H01L2924/15159 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2224/81 ,  H01L2224/83

摘要： A method for wafer level packaging includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW. Each PMR has a first height and each PSR has a second height.

摘要翻译： 一种用于晶片级封装的方法包括形成一个或多个管芯，在每个管芯上形成镀金属环（PMR），形成覆盖晶片（CW），CW具有一个或多个电镀密封环，形成体晶片（BW） BW在BW的第一侧具有空腔和金属层，将相应的管芯与CW对准，使得相应管芯上的PMR与CW上的相应的电镀密封环（PSR）对准，将PMR 在相应的芯片上相应的PSR，将BW与CW对准，使得BW的相应空腔围绕结合到CW的每个相应的芯片，并且使得BW上的金属层与CW上的至少一个PSR对准 并且将BW的第一侧上的金属层与CW上的PSR接合。 每个PMR具有第一高度，并且每个PSR具有第二高度。

公开(公告)号：US09385083B1

公开(公告)日：2016-07-05

申请号：US14720619

申请日：2015-05-22

申请人： HRL Laboratories, LLC

发明人： Florian G. Herrault ,  Melanie S. Yajima ,  Alexandros Margomenos ,  Miroslav Micovic

IPC分类号： H01L21/00 ,  H01L23/10 ,  H01L23/528 ,  H01L23/36 ,  H01L21/768 ,  H01L23/532 ,  H05K7/20

CPC分类号： H01L24/70 ,  H01L21/0273 ,  H01L21/2885 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/64 ,  H01L24/82 ,  H01L24/89 ,  H01L24/96 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/01022 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05432 ,  H01L2924/06 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H05K7/20154

摘要： An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

摘要翻译： 用于电耦合形成在相邻芯片上或邻近芯片的封装材料上的焊盘的互连，其中导电散热器设置在焊盘之间，所述互连件包括设置在两个相邻焊盘之间的金属膜层，并且设置或桥接在导电 散热器，以避免与导电散热器电接触。 电镀金属层设置在金属膜层上。 互连的制造允许使用与互连的晶片级制造兼容的制造技术来并行形成多个互连。 互连优选地遵循平滑曲线以电连接相邻的焊盘，并且遵循那些平滑的曲线，它们以可预测的方式在介于中间的导电散热器材料之间桥接。