公开(公告)号：US06831363B2

公开(公告)日：2004-12-14

申请号：US10319032

申请日：2002-12-12

申请人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

发明人： Timothy J. Dalton ,  Sanjit K. Das ,  Brett H. Engel ,  Brian W. Herbst ,  Habib Hichri ,  Bernd E. Kastenmeier ,  Kelly Malone ,  Jeffrey R. Marino ,  Arthur Martin ,  Vincent J. McGahay ,  Ian D. Melville ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant

IPC分类号： H01L2348

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

摘要翻译： 用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。 形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。 通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

公开(公告)号：US06764873B2

公开(公告)日：2004-07-20

申请号：US10199287

申请日：2002-07-18

申请人： Habib Hichri ,  Kelly Malone ,  Arthur Martin

发明人： Habib Hichri ,  Kelly Malone ,  Arthur Martin

IPC分类号： H01L5140

CPC分类号： H01L21/02203 ,  C08L71/00 ,  C09J179/08 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/312 ,  Y02P20/544 ,  Y10T428/31663 ,  Y10T428/31667 ,  Y10T428/31721

摘要： A semiconductor wafer provided with a thermosetting porous insulating film, wherein the insulating film is made porous, cured and polymerized on the wafer. The film is characterized by a very low dielectric constant based on its constituency and porosity, the latter property of which is caused by the inclusion of liquid or supercritical carbon dioxide in the polymeric reaction mixture.

摘要翻译： 提供有热固性多孔绝缘膜的半导体晶片，其中绝缘膜被制成多孔的，在晶片上固化和聚合。 该膜的特征在于基于其选区和孔隙率的非常低的介电常数，后者的特性是由于在聚合反应混合物中包含液体或超临界二氧化碳引起的。

公开(公告)号：US20120178241A1

公开(公告)日：2012-07-12

申请号：US12986266

申请日：2011-01-07

申请人： Kelly Malone ,  Habib Hichri

发明人： Kelly Malone ,  Habib Hichri

IPC分类号： H01L21/20 ,  B05D5/00 ,  H01B1/02

CPC分类号： H01B5/14 ,  H01B1/02 ,  H01B13/0026 ,  H01L21/283 ,  H01L21/76843 ,  H01L21/76871 ,  Y10T428/24999 ,  Y10T428/2982 ,  Y10T428/2989 ,  Y10T428/31663 ,  Y10T428/31678

摘要： A metal seed composition useful in seeding a metal diffusion barrier or conductive metal layer on a semiconductor or dielectric substrate, the composition comprising: a nanoscopic metal component that includes a metal useful as a metal diffusion barrier or conductive metal; an adhesive component for attaching said nanoscopic metal component on said semiconductor or dielectric substrate; and a linker component that links said nanoscopic metal component with said adhesive component. Semiconductor and dielectric substrates coated with the seed compositions, as well as methods for depositing the seed compositions, are also described.

摘要翻译： 一种金属种子组合物，其可用于在半导体或电介质基底上接种金属扩散阻挡层或导电金属层，所述组合物包括：纳米金属组分，其包含可用作金属扩散阻挡层或导电金属的金属; 用于将所述纳米金属部件附着在所述半导体或电介质基板上的粘合部件; 以及将所述纳米金属组分与所述粘合剂组分连接的连接剂组分。 还描述了涂覆有种子组合物的半导体和电介质基质以及沉积种子组合物的方法。

公开(公告)号：US20050087490A1

公开(公告)日：2005-04-28

申请号：US10695374

申请日：2003-10-28

申请人： Mark Chace ,  Jeffrey Hedrick ,  Habib Hichri ,  Keith Pope ,  Jia Lee ,  Kelly Malone ,  Kenneth McCullough ,  Wayne Moreau ,  Darryl Restaino ,  Shahab Siddiqui

发明人： Mark Chace ,  Jeffrey Hedrick ,  Habib Hichri ,  Keith Pope ,  Jia Lee ,  Kelly Malone ,  Kenneth McCullough ,  Wayne Moreau ,  Darryl Restaino ,  Shahab Siddiqui

IPC分类号： B01D11/04 ,  B01D11/00

CPC分类号： B01D11/0407

摘要： A process of removing impurities from a cured low dielectric constant organic polymeric film disposed on a semiconductor device. The process involves disposing a low dielectric constant curable organic polymeric film on an electrically conductive surface of a semiconductor device. The organic polymeric film is cured on the semiconductor device and thereupon contacted with supercritical carbon dioxide, optionally in the presence of at least one cosolvent.

摘要翻译： 从设置在半导体器件上的固化的低介电常数有机聚合物膜去除杂质的方法。 该方法包括将低介电常数可固化有机聚合物膜设置在半导体器件的导电表面上。 有机聚合物膜在半导体器件上固化，随后与超临界二氧化碳接触，任选地在至少一种助溶剂的存在下。

公开(公告)号：US08647535B2

公开(公告)日：2014-02-11

申请号：US12986266

申请日：2011-01-07

申请人： Kelly Malone ,  Habib Hichri

发明人： Kelly Malone ,  Habib Hichri

IPC分类号： H01B1/02

CPC分类号： H01B5/14 ,  H01B1/02 ,  H01B13/0026 ,  H01L21/283 ,  H01L21/76843 ,  H01L21/76871 ,  Y10T428/24999 ,  Y10T428/2982 ,  Y10T428/2989 ,  Y10T428/31663 ,  Y10T428/31678

摘要： A metal seed composition useful in seeding a metal diffusion barrier or conductive metal layer on a semiconductor or dielectric substrate, the composition comprising: a nanoscopic metal component that includes a metal useful as a metal diffusion barrier or conductive metal; an adhesive component for attaching said nanoscopic metal component on said semiconductor or dielectric substrate; and a linker component that links said nanoscopic metal component with said adhesive component. Semiconductor and dielectric substrates coated with the seed compositions, as well as methods for depositing the seed compositions, are also described.

公开(公告)号：USRE45781E1

公开(公告)日：2015-10-27

申请号：US14176526

申请日：2014-02-10

申请人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

发明人： Jeffrey C. Hedrick ,  Kang-Wook Lee ,  Kelly Malone ,  Christy S. Tyberg

IPC分类号： H01L21/02 ,  H01L23/532 ,  H01L21/70 ,  H01L23/52 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/22

CPC分类号： H01L21/22 ,  H01L21/02118 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/31663 ,  H01L2924/00

摘要： A structure useful for electrical interconnection comprises a substrate; a plurality of porous dielectric layers disposed on the substrate; an etch stop layer disposed between a first of the dielectric layers and a second of the dielectric layers; and at least one thin, tough, non-porous dielectric layer disposed between at least one of the porous dielectric layers and the etch stop layer. A method for forming the structure comprising forming a multilayer stack of porous dielectric layers on the substrate, the stack including the plurality of porous dielectric layers, and forming a plurality of patterned metal conductors within the multilayer stack. Curing of the multilayer dielectric stack may be in a single cure step in a furnace. The application and hot plate baking of the individual layers of the multi layer dielectric stack may be accomplished in a single spin-coat tool, without being removed, to fully cure the stack until all dielectric layers have been deposited.

摘要翻译： 用于电互连的结构包括：基底; 设置在所述基板上的多个多孔介电层; 设置在第一电介质层和第二介电层之间的蚀刻停止层; 以及设置在至少一个多孔电介质层和蚀刻停止层之间的至少一个薄的，韧性的无孔介电层。 一种用于形成所述结构的方法，包括在所述衬底上形成多层介电层的多层堆叠，所述堆叠包括所述多个多孔介电层，以及在所述多层堆叠内形成多个图案化的金属导体。 多层电介质堆叠的固化可以在炉中的单一固化步骤中。 多层电介质堆叠的各层的应用和热板烘烤可以在单个旋涂工具中实现，而不被去除，以完全固化堆叠，直到所有电介质层已经沉积。

公开(公告)号：US08637412B2

公开(公告)日：2014-01-28

申请号：US13214157

申请日：2011-08-19

申请人： Alfred Grill ,  Thomas Jasper Haigh, Jr. ,  Kelly Malone ,  Son Van Nguyen ,  Vishnubhai Vitthalbhai Patel ,  Hosadurga Shobha

发明人： Alfred Grill ,  Thomas Jasper Haigh, Jr. ,  Kelly Malone ,  Son Van Nguyen ,  Vishnubhai Vitthalbhai Patel ,  Hosadurga Shobha

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L29/511 ,  C08J9/26 ,  C08J2201/042 ,  C08J2383/04 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76829 ,  H01L21/76832 ,  H01L23/5329 ,  H01L29/515 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first PECVD process incorporating a silicon oxide precursor alone and then with an organo-silicon precursor with increasing flow while the flow of the silicon oxide precursor is reduced to zero provides a graded carbon adhesion layer whereby the content of C increases with layer thickness and a second PECVD process incorporating an organo-silicon precursor including an organic porogen provides a multiphase ultra-low k dielectric. The multiphase ultra-low k PECVD process uses high frequency radio frequency power just above plasma initiation in a PECVD chamber. An energy post treatment is also provided. A porous SiCOH dielectric material having a k less than 2.7 and a modulus of elasticity greater than 7 GPa is formed.

摘要翻译： 第一PECVD工艺，其单独掺入氧化硅前体，然后与有机硅前驱物同时增加流动，同时氧化硅前体的流动减少至零，从而提供渐变的碳粘附层，由此C的含量随层的厚度而增加， 结合包含有机致孔剂的有机硅前体的第二PECVD工艺提供了多相超低k电介质。 多相超低k PECVD工艺在PECVD室中使用高于等离子体起始的高频射频功率。 还提供了能量后处理。 形成k小于2.7且弹性模量大于7GPa的多孔SiCOH电介质材料。

公开(公告)号：US20080280434A1

公开(公告)日：2008-11-13

申请号：US12179054

申请日：2008-07-24

申请人： CHIH-CHAO YANG ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

发明人： CHIH-CHAO YANG ,  Griselda Bonilla ,  Shyng-Tsong Chen ,  Kelly Malone

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an enhanced interconnect structure with improved reliability. The inventive interconnect structure has enhanced mechanical strength of via contacts provided by embedded metal liners. The embedded metal liners may be continuous or discontinuous. Discontinuous embedded metal liners are provided by a discontinuous interface at the bottom of the via located within the interlayer dielectric layer.

摘要翻译： 本发明提供了一种改进的可靠性的互连结构。 本发明的互连结构具有增强的由嵌入式金属衬垫提供的通孔触点的机械强度。 嵌入的金属衬垫可以是连续的或不连续的。 不连续的嵌入式金属衬垫由位于层间介质层内的通孔底部的不连续界面提供。

公开(公告)号：US20060264036A1

公开(公告)日：2006-11-23

申请号：US11491816

申请日：2006-07-24

申请人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

发明人： Shyng-Tsong Chen ,  Stefanie Chiras ,  Matthew Colburn ,  Tomothy Dalton ,  Jeffrey Hedrick ,  Elbert Huang ,  Kaushik Kumar ,  Michael Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Nitta ,  Sampath Purushothaman ,  Robert Rosenberg ,  Christy Tyberg ,  Roy Yu

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

摘要翻译： 在多电平微电子集成电路中，空气包括永久线路电介质，超低K材料通过电介质。 在通过清洁热分解除去牺牲材料并通过IC结构中的孔隙率辅助副产物扩散后，将空气供应到线路电平。 任选地，空气也包括在通孔级电介质中的孔隙中。 通过将空气结合到本发明产生的程度，使层内和层间介电值最小化。

公开(公告)号：US20060118961A1

公开(公告)日：2006-06-08

申请号：US11341338

申请日：2006-01-26

申请人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

发明人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

IPC分类号： H01L23/48

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.