公开(公告)号：US09406531B1

公开(公告)日：2016-08-02

申请号：US14229280

申请日：2014-03-28

申请人： Zigmund Ramirez Camacho ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Dao Nguyen Phu Cuong ,  HeeJo Chi

发明人： Zigmund Ramirez Camacho ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Dao Nguyen Phu Cuong ,  HeeJo Chi

IPC分类号： H01L23/485 ,  H01L21/48 ,  H01L23/12 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L21/0335 ,  H01L21/485 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/568 ,  H01L21/76879 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05026 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

摘要翻译： 一种集成电路封装系统的制造方法及其制造方法，其特征在于，包括具有用于使所述载体露出的迹开口的光致变质介电层; 痕迹中痕迹; 直接在可光致电介质层和迹线上的内部阻焊层，内部阻焊层具有用于暴露痕迹的接合焊盘开口; 内部阻焊层上的集成电路，该集成电路通过接合焊盘开口电连接到迹线上; 直接在集成电路和内部阻焊层上的封装; 以及电耦合到迹线和集成电路的外部互连。

公开(公告)号：US09331003B1

公开(公告)日：2016-05-03

申请号：US14229538

申请日：2014-03-28

申请人： Zigmund Ramirez Camacho ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Dao Nguyen Phu Cuong ,  HeeJo Chi

发明人： Zigmund Ramirez Camacho ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Dao Nguyen Phu Cuong ,  HeeJo Chi

IPC分类号： H01L21/02 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L23/49541 ,  H01L21/4832 ,  H01L21/4846 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48248 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead islands; a device over a portion of the lead islands and having electrical connections to another portion of the lead islands, the electrical connections over areas of the another portion of the lead islands over areas covered by the pre-molded material; and an encapsulation over the device and the lead islands.

摘要翻译： 集成电路封装系统及其制造方法包括：引线岛; 围绕铅岛的底部的预成型材料; 位于引线岛的一部分上并且具有到所述引线岛的另一部分的电连接的装置，所述引线岛的另一部分的区域上的电连接在被所述预模制材料覆盖的区域上; 以及在器件和引线岛上的封装。

公开(公告)号：US09502267B1

公开(公告)日：2016-11-22

申请号：US14316190

申请日：2014-06-26

申请人： HeeJo Chi ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Zigmund Ramirez Camacho ,  Dao Nguyen Phu Cuong

发明人： HeeJo Chi ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Zigmund Ramirez Camacho ,  Dao Nguyen Phu Cuong

IPC分类号： H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L21/486 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2224/45099

摘要： An integrated circuit packaging system, and a method of manufacture thereof, includes: a support structure having: an internal insulation layer having a hole, a device connection side, and a removal mark characteristic of a conductive seed layer removed at the device connection side, a first conductive pad in the hole at the device connection side, and an exterior insulation layer over the first conductive pad at the device connection side; an integrated circuit over the exterior insulation layer; and an encapsulation over the integrated circuit.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：支撑结构，其具有：在器件连接侧除去的导电种子层的具有孔，器件连接侧和去除标记特性的内部绝缘层， 在器件连接侧的孔中的第一导电焊盘，以及在器件连接侧的第一导电焊盘上的外部绝缘层; 外部绝缘层上的集成电路; 以及集成电路上的封装。

公开(公告)号：US09406642B1

公开(公告)日：2016-08-02

申请号：US14642130

申请日：2015-03-09

申请人： HeeJo Chi ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Zigmund Ramirez Camacho ,  Dao Nguyen Phu Cuong

发明人： HeeJo Chi ,  Bartholomew Liao Chung Foh ,  Sheila Marie L. Alvarez ,  Zigmund Ramirez Camacho ,  Dao Nguyen Phu Cuong

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/12

CPC分类号： H01L24/81 ,  H01L21/4867 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/49861 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/16237 ,  H01L2224/81203 ,  H01L2224/81395 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/95 ,  H01L2924/15153 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2224/81

摘要： An integrated circuit packaging system and method of manufacture thereof includes: a substrate; a plain trace on the substrate; an insulated trace on the substrate; an insulation layer on the insulated trace, the insulation layer at least partially covers the insulated trace; and a semiconductor device over the substrate, the semiconductor device has a plain bump attached on the plain trace and an inner bump attached on the insulated trace, and the plain bump is mounted adjacent to the insulation layer.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：基板; 衬底上的平原痕迹; 衬底上的绝缘迹线; 绝缘层上的绝缘层，绝缘层至少部分覆盖绝缘迹线; 以及半导体器件，该半导体器件具有附着在平坦纹迹上的平坦凸块和附着在绝缘迹线上的内部凸起，并且平坦凸块安装在绝缘层附近。

公开(公告)号：US09355983B1

公开(公告)日：2016-05-31

申请号：US14318061

申请日：2014-06-27

申请人： Zigmund Ramirez Camacho ,  Emmanuel Espiritu ,  Bartholomew Liao Chung Foh ,  Dao Nguyen Phu Cuong ,  Jeffrey David Punzalan

发明人： Zigmund Ramirez Camacho ,  Emmanuel Espiritu ,  Bartholomew Liao Chung Foh ,  Dao Nguyen Phu Cuong ,  Jeffrey David Punzalan

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L24/25 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/562 ,  H01L24/17 ,  H01L25/04 ,  H01L2224/16225 ,  H01L2224/1701 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2924/15311 ,  H01L2924/1533

摘要： A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：支柱; 连接到支柱的导电积聚物; 以及封装导电性积聚物的成型体，该柱从成形体延伸出来。

公开(公告)号：US20160099222A1

公开(公告)日：2016-04-07

申请号：US14955033

申请日：2015-11-30

申请人： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao Chung Foh ,  Zigmund Ramirez Camacho

发明人： Il Kwon Shim ,  Kyung Moon Kim ,  HeeJo Chi ,  JunMo Koo ,  Bartholomew Liao Chung Foh ,  Zigmund Ramirez Camacho

IPC分类号： H01L23/00

CPC分类号： H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03001 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/039 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05664 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/01074 ,  H01L2224/05164 ,  H01L2224/05644 ,  H01L2224/3318

摘要： An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：提供基板; 在衬底的顶部形成接触垫; 在所述接触焊盘和所述衬底的顶部上形成保护层; 使接触垫从保护层露出; 在通过导电油墨在保护层上延伸的暴露的接触垫上印刷凸块下金属化（UBM）层; 以及在凸起下金属化层的顶部上形成凸块。 它还包括：使用导电油墨印刷粘合层，其中粘合层包括相互连接的粘合层垫; 使用电沉积工艺在所述粘附层垫的顶部上形成附加的凹凸金属化（UBM）层和凸块; 以及去除互连的粘合层垫中的连接。

公开(公告)号：US09412624B1

公开(公告)日：2016-08-09

申请号：US14316090

申请日：2014-06-26

申请人： Dao Nguyen Phu Cuong ,  Bartholomew Liao Chung Foh ,  Byung Tai Do ,  Kyung Moon Kim ,  Jeffrey David Punzalan ,  SeungYong Chai ,  Soo Won Lee ,  Kwok Keung Szeto ,  KyungOe Kim

发明人： Dao Nguyen Phu Cuong ,  Bartholomew Liao Chung Foh ,  Byung Tai Do ,  Kyung Moon Kim ,  Jeffrey David Punzalan ,  SeungYong Chai ,  Soo Won Lee ,  Kwok Keung Szeto ,  KyungOe Kim

IPC分类号： H01L29/72 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/15311

摘要： An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.

摘要翻译： 一种集成电路封装系统及其制造方法，包括：基板，包括：第一迹线层，第一迹线层上的封装，第一迹线层具有从封装暴露的表面，粗糙纹理特征为去除 导电载体涂层，在封装上和第一迹线层上的第二迹线层，第二迹线层连接到第一迹线层; 以及附接到基板的集成电路管芯。