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公开(公告)号:US20080038486A1
公开(公告)日:2008-02-14
申请号:US11833027
申请日:2007-08-02
IPC分类号: C23C16/00
CPC分类号: C23C16/401 , C23C16/4488 , C23C16/45578
摘要: A process for radical assisted film deposition simultaneously on multiple wafer substrates is provided. The multiple wafer substrates are loaded into a reactor that is heated to a desired film deposition temperature. A stable species source of oxide or nitride counter ion is introduced into the reactor. An in situ radical generating reactant is also introduced into the reactor along with a cationic ion deposition source. The cationic ion deposition source is introduced for a time sufficient to deposit a cationic ion-oxide or a cationic ion-nitride film simultaneously on multiple wafer substrates. Deposition temperature is below a conventional chemical vapor deposition temperature absent the in situ radical generating reactant. A high degree of wafer-to-wafer uniformity among the multiple wafer substrates is obtained by introducing the reactants through elongated vertical tube injectors having vertically displaced orifices, injectors surrounded by a liner having vertically displaced exhaust ports to impart across flow of movement of reactants simultaneously across the multiple wafer substrates. With molecular oxygen as a stable species source of oxide, and hydrogen as the in situ radical generating reactant, oxide films of silicon are readily produced with a silicon-containing precursor introduced into the reactor.
摘要翻译: 提供了一种在多个晶片基板上同时进行自由基辅助膜沉积的工艺。 将多个晶片衬底装载到加热到所需膜沉积温度的反应器中。 将氧化物或氮化物抗衡离子的稳定物质源引入反应器。 原位产生自由基的反应物也与阳离子离子沉积源一起引入反应器。 引入阳离子离子沉积源足以在多个晶片衬底上同时沉积阳离子氧化物或阳离子氮化物膜的时间。 沉积温度低于常规化学气相沉积温度,不存在原位产生自由基的反应物。 通过将具有垂直移位的孔的细长垂直管喷射器引入反应物,由具有垂直移位的排气口的衬套围绕的喷射器同时施加反应物的运动流动,可以获得多个晶片与晶片之间的高度的均匀性 跨越多个晶片衬底。 以分子氧作为氧化物的稳定物质来源,氢作为原位产生自由基的反应物,硅的氧化膜容易地被引入到反应器中的含硅前体产生。
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公开(公告)号:US20070010072A1
公开(公告)日:2007-01-11
申请号:US11482887
申请日:2006-07-07
申请人: Robert Bailey , Taiqing Qiu , Cole Porter , Olivier Laparra , Robert Chatham , Martin Mogaard , Helmuth Treichel
发明人: Robert Bailey , Taiqing Qiu , Cole Porter , Olivier Laparra , Robert Chatham , Martin Mogaard , Helmuth Treichel
IPC分类号: H01L21/20
CPC分类号: C23C16/54 , C23C16/308 , C23C16/345 , C23C16/402 , C23C16/45504 , C23C16/45578 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02222 , H01L21/02271 , H01L21/02274 , H01L21/3145 , H01L21/31612 , H01L21/3185
摘要: A batch of wafer substrates is provided with each wafer substrate having a surface. Each surface is coated with a layer of material applied simultaneously to the surface of each of the batch of wafer substrates. The layer of material is applied to a thickness that varies less than four thickness percent across the surface and exclusive of an edge boundary and having a wafer-to-wafer thickness variation of less than three percent. The layer of material so applied is a silicon oxide, silicon nitride or silicon oxynitride with the layer of material being devoid of carbon and chlorine. Formation of silicon oxide or a silicon oxynitride requires the inclusion of a co-reactant. Silicon nitride is also formed with the inclusion of a nitrification co-reactant. A process for forming such a batch of wafer substrates involves feeding the precursor into a reactor containing a batch of wafer substrates and reacting the precursor at a wafer substrate temperature, total pressure, and precursor flow rate sufficient to create such a layer of material. The delivery of a precursor and co-reactant as needed through vertical tube injectors having multiple orifices with at least one orifice in registry with each of the batch of wafer substrates and exit slits within the reactor to create flow across the surface of each of the wafer substrates in the batch provides the within-wafer and wafer-to-wafer uniformity.
摘要翻译: 一批晶片基板设置有每个晶片基板具有表面。 每个表面涂覆有同时施加到每批晶片衬底的表面的一层材料。 该材料层被施加到在整个表面上变化小于四个厚度百分比的厚度,而不是边缘边界,并且晶片到晶片的厚度变化小于3%。 如此施加的材料层是氧化硅,氮化硅或氮氧化硅,其中该材料层不含碳和氯。 氧化硅或氮氧化硅的形成需要包含共反应物。 氮化氮也通过包含硝化共反应物形成。 用于形成这样一批晶片衬底的方法包括将前体进料到含有一批晶片衬底的反应器中,并在足以产生这种材料层的晶片衬底温度,总压力和前体流速下使前体反应。 根据需要通过具有多个孔的垂直管注射器输送前体和共反应物,其中至少一个孔与反应器内的每批晶片基板和出口狭缝对齐,以产生跨过每个晶片的表面的流动 该批次中的衬底提供了晶片内和晶片与晶片之间的均匀性。
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公开(公告)号:US20160177439A1
公开(公告)日:2016-06-23
申请号:US14578332
申请日:2014-12-19
申请人: Yu-Chen Shen , Taiqing Qiu , Robe Woehl , Kieran Mark Tracy , Mukul Agrawal
发明人: Yu-Chen Shen , Taiqing Qiu , Robe Woehl , Kieran Mark Tracy , Mukul Agrawal
CPC分类号: C23C14/50 , C23C14/165 , C23C14/34 , C23C14/3464 , H01J37/32715
摘要: Sputter tools are described. In one embodiment, an apparatus to support a wafer includes a pallet having a depression to receive the wafer. The pallet includes an opening below the depression, and an edge in the depression is to support the wafer over the opening. A cover at least partially covers the opening. In one example, the cover may be a plate with one or more holes, and a pipe may be located below each of the holes in the cover. In one embodiment, a wafer-processing system includes a processing chamber and a pallet with a depression to receive a wafer. The pallet has an opening below the depression, and an edge in the depression supports the wafer over the opening. In one such embodiment, a cover at least partially covers the opening. According to one embodiment, an energy-absorbing material is disposed below the opening in the pallet.
摘要翻译: 描述了溅射工具。 在一个实施例中,用于支撑晶片的装置包括具有用于接收晶片的凹陷的托盘。 托盘包括在凹陷下方的开口,并且凹陷中的边缘将晶片支撑在开口上。 盖子至少部分地覆盖开口。 在一个示例中,盖可以是具有一个或多个孔的板,并且管可以位于盖中的每个孔下方。 在一个实施例中,晶片处理系统包括处理室和具有凹陷的托盘以接收晶片。 托盘在凹陷下方具有开口,并且凹陷中的边缘将晶片支撑在开口上方。 在一个这样的实施例中,盖至少部分地覆盖开口。 根据一个实施例,能量吸收材料设置在托盘中的开口下方。
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公开(公告)号:US06300600B1
公开(公告)日:2001-10-09
申请号:US09373894
申请日:1999-08-12
IPC分类号: F27B514
CPC分类号: C23C16/463 , C23C16/455 , C23C16/4584 , C30B25/10 , C30B25/14 , F27B5/14 , F27B2005/161 , F27D1/1858 , F27D2003/0075 , H01L21/67109
摘要: An apparatus for heat treatment of a wafer is disclosed. The apparatus includes a heating chamber having a heat source. A cooling chamber is positioned adjacent to the heating chamber and includes a cooling source. A wafer holder is configured to move between the cooling chamber and the heating chamber through a passageway and one or more shutters defines the size of the passageway. The one or more shutters are movable between an open position where the wafer holder can pass through the passageway and an obstructing position which defines a passageway which is smaller than the passageway defined when the shutter is in the open position.
摘要翻译: 公开了一种用于晶片热处理的设备。 该装置包括具有热源的加热室。 冷却室位于加热室附近并且包括冷却源。 晶片保持器构造成通过通道在冷却室和加热室之间移动,并且一个或多个快门限定通道的尺寸。 一个或多个百叶窗可以在晶片保持器可以穿过通道的打开位置和限定通道的阻塞位置之间移动,该通道小于当快门处于打开位置时所限定的通道。
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5.
公开(公告)号:US20170222072A1
公开(公告)日:2017-08-03
申请号:US15493021
申请日:2017-04-20
申请人: Seung Bum Rim , David D. Smith , Taiqing Qiu , Staffan Westerberg , Kieran Mark Tracy , Venkatasubramani Balu
发明人: Seung Bum Rim , David D. Smith , Taiqing Qiu , Staffan Westerberg , Kieran Mark Tracy , Venkatasubramani Balu
IPC分类号: H01L31/0224 , H01L31/0216 , H01L31/0236 , H01L31/18 , H01L31/0368
CPC分类号: H01L31/022441 , H01L31/02167 , H01L31/02168 , H01L31/02363 , H01L31/03682 , H01L31/068 , H01L31/0682 , H01L31/0745 , H01L31/0747 , H01L31/1804 , H01L31/182 , H01L31/202 , H01L31/208 , Y02E10/547 , Y02P70/521
摘要: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.
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公开(公告)号:US09559245B2
公开(公告)日:2017-01-31
申请号:US14747874
申请日:2015-06-23
申请人: Taiqing Qiu , Gilles Olav Tanguy Sylvain Poulain , Périne Jaffrennou , Nada Habka , Sergej Filonovich
发明人: Taiqing Qiu , Gilles Olav Tanguy Sylvain Poulain , Périne Jaffrennou , Nada Habka , Sergej Filonovich
IPC分类号: H01L31/18
CPC分类号: H01L31/0682 , H01L31/02008 , H01L31/02167 , H01L31/022441 , H01L31/02363 , H01L31/03682 , H01L31/1804 , H01L31/182 , H01L31/1824 , H01L31/1864 , H01L31/1872 , Y02E10/545 , Y02E10/547 , Y02P70/521
摘要: Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.
摘要翻译: 这里描述的是制造太阳能电池的方法。 在一个示例中,制造太阳能电池的方法包括在与基板的光接收表面相对的基板的背面上形成非晶介质层。 该方法还包括通过等离子体增强化学气相沉积(PECVD)在非晶介质层上形成微晶硅层。 该方法还包括通过PECVD在微晶硅层上形成非晶硅层。 该方法还包括退火微晶硅层和非晶硅层,以从微晶硅层和非晶硅层形成均匀的多晶硅层。 该方法还包括从均质多晶硅层形成发射极区域。
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公开(公告)号:US06900413B2
公开(公告)日:2005-05-31
申请号:US10261963
申请日:2002-09-30
IPC分类号: C23C16/455 , C23C16/458 , C30B25/10 , C30B25/14 , F27B5/14 , F27B5/16 , F27D1/18 , F27D3/00 , H01L21/00
CPC分类号: C23C16/463 , C23C16/455 , C23C16/4584 , C30B25/10 , C30B25/14 , F27B5/14 , F27B2005/161 , F27D1/1858 , F27D2003/0075 , H01L21/67109
摘要: An apparatus for heat treatment of a wafer is disclosed. The apparatus includes a heating chamber having a heat source. A cooling chamber is positioned adjacent to the heating chamber and includes a cooling source. A wafer holder is configured to move between the cooling chamber and the heating chamber through a passageway and one or more shutters defines the size of the passageway. The one or more shutters are movable between an open position where the wafer holder can pass through the passageway and an obstructing position which defines a passageway which is smaller than the passageway defined when the shutter is in the open position.
摘要翻译: 公开了一种用于晶片热处理的设备。 该装置包括具有热源的加热室。 冷却室位于加热室附近并且包括冷却源。 晶片保持器构造成通过通道在冷却室和加热室之间移动,并且一个或多个快门限定通道的尺寸。 一个或多个百叶窗可以在晶片保持器可以穿过通道的打开位置和限定通道的阻塞位置之间移动,该通道小于当快门处于打开位置时限定的通道。
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8.
公开(公告)号:US09634177B2
公开(公告)日:2017-04-25
申请号:US14919049
申请日:2015-10-21
申请人: Seung Bum Rim , David D. Smith , Taiqing Qiu , Staffan Westerberg , Kieran Mark Tracy , Venkatasubramani Balu
发明人: Seung Bum Rim , David D. Smith , Taiqing Qiu , Staffan Westerberg , Kieran Mark Tracy , Venkatasubramani Balu
IPC分类号: H01L31/18 , H01L31/0224 , H01L31/068 , H01L31/20 , H01L31/0236 , H01L31/0368 , H01L31/0216 , H01L31/0745 , H01L31/0747
CPC分类号: H01L31/022441 , H01L31/02167 , H01L31/02168 , H01L31/02363 , H01L31/03682 , H01L31/068 , H01L31/0682 , H01L31/0745 , H01L31/0747 , H01L31/1804 , H01L31/182 , H01L31/202 , H01L31/208 , Y02E10/547 , Y02P70/521
摘要: Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.
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公开(公告)号:US09564854B2
公开(公告)日:2017-02-07
申请号:US14705268
申请日:2015-05-06
申请人: Xiuwen Tu , David Aitan Soltz , Michael C. Johnson , Seung Bum Rim , Taiqing Qiu , Yu-Chen Shen , Kieran Mark Tracy
发明人: Xiuwen Tu , David Aitan Soltz , Michael C. Johnson , Seung Bum Rim , Taiqing Qiu , Yu-Chen Shen , Kieran Mark Tracy
CPC分类号: H02S50/15 , G01N21/6408 , G01N21/6489 , G01N2201/06113 , G01N2201/0621
摘要: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.
摘要翻译: 对半导体测试方法和半导体测试设备进行描述。 在一个示例中,用于测试半导体的方法可以包括在半导体上施加光以引起光子降解。 该方法还可以包括接收从半导体施加的光引起的光致发光测量,并从光致发光测量监测半导体的光子劣化。
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公开(公告)号:US20160329864A1
公开(公告)日:2016-11-10
申请号:US14705268
申请日:2015-05-06
申请人: Xiuwen Tu , David Aitan Soltz , Michael C. Johnson , Seung Bum Rim , Taiqing Qiu , Yu-Chen Shen , Kieran Mark Tracy
发明人: Xiuwen Tu , David Aitan Soltz , Michael C. Johnson , Seung Bum Rim , Taiqing Qiu , Yu-Chen Shen , Kieran Mark Tracy
CPC分类号: H02S50/15 , G01N21/6408 , G01N21/6489 , G01N2201/06113 , G01N2201/0621
摘要: Methods of testing a semiconductor, and semiconductor testing apparatus, are described. In an example, a method for testing a semiconductor can include applying light on the semiconductor to induce photonic degradation. The method can also include receiving a photoluminescence measurement induced from the applied light from the semiconductor and monitoring the photonic degradation of the semiconductor from the photoluminescence measurement.
摘要翻译: 对半导体测试方法和半导体测试设备进行描述。 在一个示例中,用于测试半导体的方法可以包括在半导体上施加光以引起光子降解。 该方法还可以包括接收从半导体施加的光引起的光致发光测量,并从光致发光测量监测半导体的光子劣化。
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