公开(公告)号：US08685792B2

公开(公告)日：2014-04-01

申请号：US12040558

申请日：2008-02-29

申请人： Seng Guan Chow ,  Il Kwon Shim

发明人： Seng Guan Chow ,  Il Kwon Shim

IPC分类号： H01L23/498

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit package system includes: providing a mountable integrated circuit system having an encapsulation with a cavity therein and a first interposer exposed by the cavity; mounting a second interposer over the first interposer for only stacking a discrete device thereover, and with the second interposer over the encapsulation and the cavity; and mounting an electrical component over the second interposer.

摘要翻译： 集成电路封装系统包括：提供具有其中具有空腔的封装的可安装集成电路系统和由腔暴露的第一插入器; 在第一插入器上安装第二插入件，仅在其上堆叠分立器件，并且第二插入器穿过封装和空腔; 并将电气部件安装在第二插入件上。

公开(公告)号：US08558399B2

公开(公告)日：2013-10-15

申请号：US13443067

申请日：2012-04-10

申请人： Kambhampati Ramakrishna ,  Il Kwon Shim ,  Seng Guan Chow

发明人： Kambhampati Ramakrishna ,  Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L23/28

CPC分类号： H01L23/3128 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/165 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.

摘要翻译： 提供了一种双模塑多芯片封装系统，包括形成嵌入式集成电路封装系统，其具有部分覆盖第一集成电路管芯的第一封装和与其连接的引线，将半导体器件安装在第一封装上并连接到引线上，以及 在半导体器件和嵌入式集成电路封装系统上形成第二封装。

公开(公告)号：US08354746B2

公开(公告)日：2013-01-15

申请号：US13174033

申请日：2011-06-30

申请人： Rui Huang ,  Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Rui Huang ,  Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L21/00

CPC分类号： H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.

摘要翻译： 使用包括基板和多个导电柱的预制柱载体制成半导体封装。 胶片密封剂设置在柱载体的基板上并且在导电柱周围。 半导体管芯安装到临时载体上。 将载体和临时载体压在一起以将半导体管芯嵌入膜密封剂中。 半导体管芯设置在膜密封剂的导电柱之间。 卸载载体的临时载体和基板。 在膜密封剂的第一侧上形成第一电路堆积层。 第一电路堆积层电连接到导电柱。 第二电路堆积层形成在与第一侧相对的膜密封剂的第二侧上。 第二电路堆积层电连接到导电柱。

公开(公告)号：US08143107B2

公开(公告)日：2012-03-27

申请号：US12715910

申请日：2010-03-02

申请人： Byung Tai Do ,  Il Kwon Shim ,  Seng Guan Chow

发明人： Byung Tai Do ,  Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method of manufacture of an integrated circuit packaging system includes: forming a substrate including: patterning a bonding pad on the substrate, patterning a first signal trace coupled to the bonding pad, patterning a second signal trace on the substrate, and connecting a pedestal on the second signal trace; mounting an integrated circuit on the substrate; and coupling an electrical interconnect between the integrated circuit, the bonding pad, the pedestal, or a combination thereof.

摘要翻译： 一种集成电路封装系统的制造方法，包括：形成衬底，包括：将衬底上的焊盘图案化，图案化耦合到焊盘的第一信号迹线，对衬底上的第二信号迹线进行图案化，以及将衬底 第二信号迹线; 在基板上安装集成电路; 并且耦合集成电路，接合焊盘，基座之间的电互连或其组合。

公开(公告)号：US20110306168A1

公开(公告)日：2011-12-15

申请号：US13217239

申请日：2011-08-24

申请人： Rajendra D. Pendse ,  Flynn Carson ,  Il Kwon Shim ,  Seng Guan Chow

发明人： Rajendra D. Pendse ,  Flynn Carson ,  Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L21/56

CPC分类号： H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system and method of manufacture thereof includes: forming an area array substrate; mounting surface conductors on the area array substrate; and molding a molded package body, having a step surrounding a core section, on the area array substrate and the surface conductors, the step providing access to the surface conductors including providing a non-vertical slope from the core section to the step.

摘要翻译： 集成电路封装系统及其制造方法包括：形成区域阵列基板; 在面阵列基板上安装表面导体; 并且在所述区域阵列基板和所述表面导体上模制具有围绕芯部的台阶的模制封装体，所述台阶提供对所述表面导体的访问，所述台阶导体包括提供从所述芯部到所述台阶的非垂直斜率。

公开(公告)号：US08072059B2

公开(公告)日：2011-12-06

申请号：US12476447

申请日：2009-06-02

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin ,  Rui Huang

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin ,  Rui Huang

IPC分类号： H01L23/04

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1902 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is made by forming a first conductive layer over a temporary carrier. A UBM layer is formed over the temporary carrier and fixed in position relative to the first conductive layer. A conductive pillar is formed over the first conductive layer. A semiconductor die is mounted to the UBM layer to align the die relative to the conductive pillar. An encapsulant is deposited over the die and around the conductive pillar. The UBM layer prevents shifting of the semiconductor die while depositing the encapsulant. The temporary carrier is removed. A first interconnect structure is formed over a first surface of the encapsulant. A second interconnect structure is formed over a second surface of the encapsulant. The first and second interconnect structures are electrically connected through the conductive pillar. The first or second interconnect structure includes an integrated passive device electrically connected to the conductive pillar.

摘要翻译： 通过在临时载体上形成第一导电层制成半导体器件。 UBM层形成在临时载体上并相对于第一导电层固定在适当位置。 在第一导电层上形成导电柱。 将半导体管芯安装到UBM层上以相对于导电柱对准管芯。 密封剂沉积在模具上并且围绕导电柱。 UBM层防止半导体管芯移动，同时沉积密封剂。 移除临时载体。 在密封剂的第一表面上形成第一互连结构。 在密封剂的第二表面上形成第二互连结构。 第一和第二互连结构通过导电柱电连接。 第一或第二互连结构包括电连接到导电柱的集成无源器件。

公开(公告)号：US08050047B2

公开(公告)日：2011-11-01

申请号：US12136002

申请日：2008-06-09

申请人： Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna

发明人： Seng Guan Chow ,  Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna

IPC分类号： H05K1/16 ,  H05K1/00 ,  H01L23/02

CPC分类号： H01L25/105 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： An integrated circuit package system includes: providing a flexible circuit substrate having a fold; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a recessed encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover.

摘要翻译： 集成电路封装系统包括：提供具有折叠的柔性电路基板; 在柔性电路基板上安装集成电路或集成电路封装，并用互连连接到柔性电路基板; 以及用具有第一电平和第二电平的凹入封装封装所述集成电路或集成电路封装，所述第二电平具有在其上折叠的所述柔性电路基板。

公开(公告)号：US08034661B2

公开(公告)日：2011-10-11

申请号：US12625975

申请日：2009-11-25

申请人： Yaojian Lin ,  Il Kwon Shim ,  Seng Guan Chow

发明人： Yaojian Lin ,  Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/552 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.

摘要翻译： 半导体器件具有在指定用于凸块形成的位置中安装到临时衬底的应力释放缓冲器。 应力消除缓冲器可以是多层复合材料，例如第一顺应层，在第一柔性层上形成的硅层，以及形成在硅层上的第二柔性层。 半导体管芯也安装在临时衬底上。 应力消除缓冲器可以比半导体管芯更薄。 密封剂沉积在半导体管芯和应力释放缓冲器之间。 移除临时衬底。 在半导体管芯，密封剂和应力释放缓冲器上形成互连结构。 互连结构电连接到半导体管芯。 可以在应力消除缓冲器和密封剂上形成加强层。 可以在应力消除缓冲器内形成包含有源器件，无源器件，导电层和电介质层的电路层。

公开(公告)号：US20110233744A1

公开(公告)日：2011-09-29

申请号：US13154308

申请日：2011-06-06

申请人： Seng Guan Chow ,  Ming Ying ,  Il Kwon Shim ,  Roger Emigh

发明人： Seng Guan Chow ,  Ming Ying ,  Il Kwon Shim ,  Roger Emigh

IPC分类号： H01L23/495 ,  H01L21/60 ,  H01L21/98

CPC分类号： H01L21/565 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for manufacturing an integrated circuit package system includes: providing a leadframe; forming a protruding pad on the leadframe; attaching a die to the leadframe; electrically connecting the die to the leadframe; and encapsulating at least portions of the leadframe, the protruding pad, and the die in an encapsulant.

摘要翻译： 一种用于制造集成电路封装系统的方法，包括：提供引线框架; 在引线框上形成突出的焊盘; 将模具附接到引线框架; 将管芯电连接到引线框架; 并且将引线框，突出垫和模具的至少一部分封装在密封剂中。

公开(公告)号：US20110147926A1

公开(公告)日：2011-06-23

申请号：US13038843

申请日：2011-03-02

申请人： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

发明人： Il Kwon Shim ,  Yaojian Lin ,  Seng Guan Chow

IPC分类号： H01L23/485

CPC分类号： H05K1/185 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/187 ,  H05K3/205 ,  H05K3/4644 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a first semiconductor die or component having a plurality of bumps, and a plurality of first and second contact pads. In one embodiment, the first and second contact pads include wettable contact pads. The bumps are mounted directly to a first surface of the first contact pads to align the first semiconductor die or component. An encapsulant is deposited over the first semiconductor die or component. An interconnect structure is formed over the encapsulant and is connected to a second surface of the first and second contact pads opposite the first surface of the first contact pads. A plurality of vias is formed through the encapsulant and extends to a first surface of the second contact pads. A conductive material is deposited in the vias to form a plurality of conductive vias that are aligned by the second contact pads to reduce interconnect pitch.

摘要翻译： 半导体器件包括具有多个凸块的第一半导体管芯或部件，以及多个第一和第二接触焊盘。 在一个实施例中，第一和第二接触垫包括可湿性接触垫。 凸块直接安装在第一接触焊盘的第一表面上，以对准第一半导体管芯或部件。 密封剂沉积在第一半导体管芯或部件上。 互连结构形成在密封剂上方并连接到与第一接触焊盘的第一表面相对的第一和第二接触焊盘的第二表面。 通过密封剂形成多个通孔并且延伸到第二接触焊盘的第一表面。 导电材料沉积在通孔中以形成多个导电通孔，其通过第二接触焊盘对准以减少互连间距。