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    Integrated method for release and passivation of MEMS structures
    1.
    发明授权
    Integrated method for release and passivation of MEMS structures 失效
    MEMS结构的释放和钝化的集成方法

    公开(公告)号：US06902947B2

    公开(公告)日：2005-06-07

    申请号：US10435757

    申请日：2003-05-09

    申请人： Jeffrey D. Chinn ,  Rolf A. Guenther ,  Michael B. Rattner ,  James A. Cooper ,  Toi Yue Becky Leung ,  Claes H. Bjorkman

    发明人： Jeffrey D. Chinn ,  Rolf A. Guenther ,  Michael B. Rattner ,  James A. Cooper ,  Toi Yue Becky Leung ,  Claes H. Bjorkman

    IPC分类号： B81B3/00 ,  B81C1/00 ,  H01L21/00

    CPC分类号： B81C1/0096 ,  B81B3/0005 ,  B81C2201/0176 ,  B81C2201/112 ,  B82Y30/00

    摘要： Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises treating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures which may be adjusted to be carried out in a either a single chamber processing system or a multi-chamber processing system.

    摘要翻译： 本文公开了一种改进疏水性自组装单层（SAM）涂层到MEMS结构表面的粘附性的方法，以防止粘结。 该方法包括用包含氧气和任选的氢气的源气体产生的等离子体处理MEMS结构的表面。 处理氧化表面，然后与氢气反应以在表面上形成键合的OH基团。 氢源可以作为等离子体源气体的一部分存在，使得在用等离子体处理表面期间产生结合的OH基团。 本文还公开了一种用于MEMS结构的释放和钝化的集成方法，其可以被调整为在单室处理系统或多室处理系统中进行。

    Ashable layers for reducing critical dimensions of integrated circuit features
    2.
    发明授权
    Ashable layers for reducing critical dimensions of integrated circuit features 失效
    用于降低集成电路特性的关键尺寸的可铺层

    公开(公告)号：US07105442B2

    公开(公告)日：2006-09-12

    申请号：US10154532

    申请日：2002-05-22

    申请人： Hongching Shan ,  Kenny L. Doan ,  Jingbao Liu ,  Michael S. Barnes ,  Hong D. Nguyen ,  Christopher Dennis Bencher ,  Christopher S. Ngai ,  Wendy H. Yeh ,  Eda Tuncel ,  Claes H. Bjorkman

    发明人： Hongching Shan ,  Kenny L. Doan ,  Jingbao Liu ,  Michael S. Barnes ,  Hong D. Nguyen ,  Christopher Dennis Bencher ,  Christopher S. Ngai ,  Wendy H. Yeh ,  Eda Tuncel ,  Claes H. Bjorkman

    IPC分类号： H01L21/44 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/31144 ,  G03F7/40 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31116 ,  H01L21/312 ,  H01L21/3146

    摘要： A method is described for decreasing the critical dimensions of integrated circuit features in which a first masking layer (101) is deposited, patterned and opened in the manner of typical feature etching, and a second masking layer (201) is deposited thereon prior to etching the underlying insulator. The second masking layer is advantageously coated in a substantially conformal manner. Opening the second masking layer while leaving material of the second layer on the sidewalls of the first masking layer as spacers leads to reduction of the feature critical dimension in the underlying insulator. Ashable masking materials, including amorphous carbon and organic materials are removable without CMP, thereby reducing costs. Favorable results are also obtained utilizing more than one masking layer (101, 301) underlying the topmost masking layer (302) from which the spacers are formed. Embodiments are also described in which slope etching replaces the addition of a separate spacer layer. Substructures formed in the fabrication process are also described. Spacers are also shown to be favorably employed in making feature-in-feature structures.

    摘要翻译： 描述了一种降低集成电路特征的关键尺寸的方法，其中以典型特征蚀刻的方式沉积，图案化和打开第一掩模层（101），并且在蚀刻之前沉积第二掩模层（201） 底层绝缘子。 有利地以基本上共形的方式涂覆第二掩模层。 打开第二掩蔽层，同时将第二层的材料留在第一掩模层的侧壁上作为间隔物导致下层绝缘体中的特征临界尺寸的减小。 包括无定形碳和有机材料在内的可湿性掩蔽材料可以不经CMP去除，从而降低成本。 利用形成间隔物的最上面的掩模层（302）下方的多于一个掩模层（101,301）也可获得有利的结果。 还描述了其中斜率蚀刻替代单独的间隔层的添加的实施例。 还描述了在制造过程中形成的子结构。 垫片也被用于制造特征特征结构。

    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
    6.
    发明授权
    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene 失效
    系统级原位集成电介质蚀刻工艺特别适用于铜双镶嵌

    公开(公告)号：US06500357B1

    公开(公告)日：2002-12-31

    申请号：US09538443

    申请日：2000-03-29

    申请人： Lee Luo ,  Claes H. Bjorkman ,  Brian Sy Yuan Shieh ,  Gerald Zheyao Yin

    发明人： Lee Luo ,  Claes H. Bjorkman ,  Brian Sy Yuan Shieh ,  Gerald Zheyao Yin

    IPC分类号： H01L21302

    CPC分类号： H01L21/67167 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/67213 ,  H01L21/6723 ,  H01L21/76807

    摘要： An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a stop layer and a feature in the substrate to be contacted into the first etching chamber to etch the dielectric layer. The substrate is then transferred from the first etching chamber to the second etching chamber under vacuum conditions and, in the second etching chamber, is exposed to an oxygen plasma or similar environment to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the stop layer is etched through to the feature to be contacted in either the second or a third etching chamber of said multichamber substrate processing system. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps.

    摘要翻译： 在具有第一和第二蚀刻室的多室基板处理系统中执行的集成原位蚀刻工艺。 该工艺包括将在其上形成的衬底沿着向下的方向转印图案化的光致抗蚀剂掩模，介电层，停止层和衬底中的要接触第一蚀刻室的特征，以蚀刻电介质层。 然后在真空条件下将衬底从第一蚀刻室转移到第二蚀刻室，并且在第二蚀刻室中暴露于氧等离子体或类似环境以剥离沉积在衬底上的光致抗蚀剂掩模。 在剥离光致抗蚀剂掩模之后，将停止层蚀刻到要在多室基板处理系统的第二或第三蚀刻室中接触的特征。 所有三个蚀刻步骤都是在系统级原位工艺中进行的，因此基板不会在台阶之间暴露于环境中。

    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
    10.
    发明授权
    System level in-situ integrated dielectric etch process particularly useful for copper dual damascene 失效
    系统级原位集成电介质蚀刻工艺特别适用于铜双镶嵌

    公开(公告)号：US06949203B2

    公开(公告)日：2005-09-27

    申请号：US10379439

    申请日：2003-03-03

    申请人： Chang-Lin Hsieh ,  Diana Xiaobing Ma ,  Brian Sy Yuan Shieh ,  Gerald Zheyao Yin ,  Jennifer Sun ,  Senh Thach ,  Lee Luo ,  Claes H. Bjorkman

    发明人： Chang-Lin Hsieh ,  Diana Xiaobing Ma ,  Brian Sy Yuan Shieh ,  Gerald Zheyao Yin ,  Jennifer Sun ,  Senh Thach ,  Lee Luo ,  Claes H. Bjorkman

    IPC分类号： H01L21/00 ,  H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/76832 ,  H01J37/32458 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/67219 ,  H01L21/6723 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807

    摘要： An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate. After the photoresist mask is stripped, the barrier layer is etched through to the feature to be contacted in the second chamber of the multichamber substrate processing system using a process that discourages polymer formation over the relatively smooth interior surface of the second chamber. All three etching steps are performed in a system level in situ process so that the substrate is not exposed to an ambient between steps. In some embodiments the interior surface of the first chamber has a roughness between 100 and 200 Ra and in other embodiments the roughness of the first chamber's interior surface is between 110 and 160 Ra.

    摘要翻译： 在具有第一和第二蚀刻室的多室衬底处理系统中执行的集成原位蚀刻工艺。 在一个实施例中，第一室包括已经被粗糙化至少100个的内表面，而第二室包括具有小于约32μm的粗糙度的内表面， / SUB>。 该方法包括在向下的方向上转移其上形成有图案的光致抗蚀剂掩模，电介质层，阻挡层和衬底中的特征的衬底，以接触第一室，其中介电层被刻蚀在鼓励聚合物的过程中 在室的粗糙内表面上形成。 然后在真空条件下将衬底从第一室转移到第二室，并且在第二室中暴露于诸如氧的反应性等离子体以剥离沉积在衬底上的光致抗蚀剂掩模。 在光致抗蚀剂掩模被剥离之后，通过阻止在第二室的相对光滑的内表面上聚合物形成的工艺，阻挡层被蚀刻到多室基板处理系统的第二室中以接触的特征。 所有三个蚀刻步骤都是在系统级原位工艺中进行的，因此基板不会在台阶之间暴露于环境中。 在一些实施例中，第一室的内表面具有在100和200之间的粗糙度，而在其它实施例中，第一室的内表面的粗糙度在110和160之间， SUB>。