公开(公告)号：US20070246133A1

公开(公告)日：2007-10-25

申请号：US10580740

申请日：2004-11-17

申请人： Johann Helneder ,  Holger Torwesten

发明人： Johann Helneder ,  Holger Torwesten

IPC分类号： C25D7/00

CPC分类号： H01L24/11 ,  H01L21/2885 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method for electroplating is provided in which a copper layer is patterned using a resist. A barrier layer lies below the copper layer and is used to supply the electroplating current in regions without the copper layer. The method makes it possible to produce high-quality soldering bumps.

摘要翻译： 提供了一种电镀方法，其中使用抗蚀剂对铜层进行图案化。 阻挡层位于铜层的下方，用于在没有铜层的区域中提供电镀电流。 该方法可以生产高质量的焊锡凸块。

公开(公告)号：US20060214265A1

公开(公告)日：2006-09-28

申请号：US11368254

申请日：2006-03-03

申请人： Thomas Goebel ,  Johann Helneder ,  Heinrich Korner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

发明人： Thomas Goebel ,  Johann Helneder ,  Heinrich Korner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

IPC分类号： H01L29/00

CPC分类号： H01L28/40 ,  H01L21/31687 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

公开(公告)号：US20100129977A1

公开(公告)日：2010-05-27

申请号：US12696811

申请日：2010-01-29

申请人： Thomas Goebel ,  Johann Helneder ,  Heinrich Körner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

发明人： Thomas Goebel ,  Johann Helneder ,  Heinrich Körner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

IPC分类号： H01L21/77 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L21/31687 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

摘要翻译： 提出了一种集成电路和制造方法。 集成电路包括在基极和覆盖电极之间包含基极，覆盖电极和电介质的电容器。 电介质包含可以通过阳极氧化产生的基极中包含的材料的氧化物。 电介质的外围边缘被覆盖电极覆盖。 电容器上的基极层包括与电介质相邻的切口。 在制造过程中，基层保护待化学物质被阳极氧化的基底材料，并且保护周围区域免受阳极氧化。 可以与电容器同时制造精密电阻器。

公开(公告)号：US20070114662A1

公开(公告)日：2007-05-24

申请号：US11600694

申请日：2006-11-16

申请人： Johann Helneder ,  Manfred Schneegans ,  Holger Torwesten

发明人： Johann Helneder ,  Manfred Schneegans ,  Holger Torwesten

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L24/12 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/8121 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

摘要： One aspect of the invention relates to an interconnecting element between a semiconductor chip of a semiconductor wafer and a circuit support and to a method for producing and using the interconnecting element. Such interconnecting elements are arranged between contact areas of a semiconductor chip of a semiconductor wafer and contact terminal areas of a circuit support. The contact areas on the semiconductor chip or the semiconductor wafer, respectively, are arranged in depressions of a top of an insulating cover layer and are freely accessible. The interconnecting elements have a mushroom shape with a mushroom cap in a first metal area. On the mushroom cap of the first metal area, a second metal area is arranged which has high-melting intermetallic phases of metals of a solder material and the metal of the contact terminal areas of the circuit support.

摘要翻译： 本发明的一个方面涉及半导体晶片的半导体芯片和电路支架之间的互连元件以及用于制造和使用互连元件的方法。 这种互连元件被布置在半导体晶片的半导体芯片的接触区域和电路支架的接触端子区域之间。 分别在半导体芯片或半导体晶片上的接触区域设置在绝缘覆盖层的顶部的凹部中并且可以自由接近。 互连元件具有在第一金属区域中具有蘑菇帽的蘑菇形状。 在第一金属区域的蘑菇帽上，布置有第二金属区域，其具有焊料材料的金属的高熔点金属间相和电路支撑体的接触端子区域的金属。

公开(公告)号：US08367514B2

公开(公告)日：2013-02-05

申请号：US12696811

申请日：2010-01-29

申请人： Thomas Goebel ,  Johann Helneder ,  Heinrich Körner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

发明人： Thomas Goebel ,  Johann Helneder ,  Heinrich Körner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

IPC分类号： H01L21/302

CPC分类号： H01L28/40 ,  H01L21/31687 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

摘要翻译： 提出了一种集成电路和制造方法。 集成电路包括在基极和覆盖电极之间包含基极，覆盖电极和电介质的电容器。 电介质包含可以通过阳极氧化产生的基极中包含的材料的氧化物。 电介质的外围边缘被覆盖电极覆盖。 电容器上的基极层包括与电介质相邻的切口。 在制造过程中，基层保护待化学物质被阳极氧化的基底材料，并且保护周围区域免受阳极氧化。 可以与电容器同时制造精密电阻器。

公开(公告)号：US07692266B2

公开(公告)日：2010-04-06

申请号：US11368254

申请日：2006-03-03

申请人： Thomas Goebel ,  Johann Helneder ,  Heinrich Körner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

发明人： Thomas Goebel ,  Johann Helneder ,  Heinrich Körner ,  Andrea Mitchell ,  Markus Schwerd ,  Martin Seck ,  Holger Torwesten

IPC分类号： H01L29/43

CPC分类号： H01L28/40 ,  H01L21/31687 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/016 ,  H01L27/0802 ,  H01L27/0805 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

摘要翻译： 提出了一种集成电路和制造方法。 集成电路包括在基极和覆盖电极之间包含基极，覆盖电极和电介质的电容器。 电介质包含可以通过阳极氧化产生的基极中包含的材料的氧化物。 电介质的外围边缘被覆盖电极覆盖。 电容器上的基极层包括与电介质相邻的切口。 在制造过程中，基层保护待化学物质被阳极氧化的基底材料，并且保护周围区域免受阳极氧化。 可以与电容器同时制造精密电阻器。

公开(公告)号：US20130005144A1

公开(公告)日：2013-01-03

申请号：US13610268

申请日：2012-09-11

申请人： Manfred Schneegans ,  Holger Torwesten

发明人： Manfred Schneegans ,  Holger Torwesten

IPC分类号： H01L21/768

CPC分类号： H01L23/53238 ,  H01L24/03 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11906 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/19042 ,  H01L2924/00014

摘要： An electronic device is disclosed. In one embodiment, the electronic device includes a substrate, a plurality of conducting lines formed on a first conducting material that is disposed on the substrate, and a layer of a second conducting material disposed on the plurality of conducting lines. The conducting lines include a top face and a side face. The layer of the second conducting material includes a first thickness disposed on each of the top faces and a second thickness disposed on each of the side faces. To this end, the first thickness is greater than the second thickness.

摘要翻译： 公开了一种电子设备。 在一个实施例中，电子设备包括衬底，形成在设置在衬底上的第一导电材料上的多条导电线和设置在多条导线上的第二导电材料层。 导线包括顶面和侧面。 第二导电材料的层包括设置在每个顶面上的第一厚度和设置在每个侧面上的第二厚度。 为此，第一厚度大于第二厚度。

公开(公告)号：US08263491B2

公开(公告)日：2012-09-11

申请号：US11875711

申请日：2007-10-19

申请人： Florian Binder ,  Stephan Dertinger ,  Barbara Hasler ,  Alfred Martin ,  Grit Sommer ,  Holger Torwesten

发明人： Florian Binder ,  Stephan Dertinger ,  Barbara Hasler ,  Alfred Martin ,  Grit Sommer ,  Holger Torwesten

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/486 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/04941 ,  H01L2924/078 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A substrate has at least one feedthrough with at least one channel from a first main surface of the substrate to a second main surface of the substrate. The at least one channel is closed off with a first material. The at least one closed-off channel is filled with an electrically conductive second material.

摘要翻译： 衬底具有至少一个馈通，其具有从衬底的第一主表面到衬底的第二主表面的至少一个通道。 至少一个通道用第一材料封闭。 至少一个闭合通道填充有导电的第二材料。

公开(公告)号：US20080230905A1

公开(公告)日：2008-09-25

申请号：US11688050

申请日：2007-03-19

申请人： Karsten Guth ,  Holger Torwesten

发明人： Karsten Guth ,  Holger Torwesten

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/32 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29147 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45647 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/8383 ,  H01L2224/83948 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1517 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： In a power semiconductor module, a copper-containing first soldering partner, a connection layer, and a copper-containing second soldering partner are arranged successively and fixedly connected with one another. The connection layer has a portion of intermetallic copper-tin phases of at least 90% by weight. For producing such a power semiconductor module the soldering partners and the solder arranged there between are pressed against one another with a predefined pressure and the solder is melted. After termination of a predefined period of time the diffused copper and the tin from the liquid solder form a connection layer comprising intermetallic copper-tin phases, the portion of which is at least 90% by weight of the connection layer created from the solder layer.

摘要翻译： 在功率半导体模块中，连续并且固定地连接有含铜的第一焊接对象，连接层和含铜的第二焊接对象。 连接层具有至少90重量％的金属间铜 - 锡相的一部分。 为了制造这样的功率半导体模块，焊接对象和布置在其间的焊料彼此以预定压力彼此压紧，并且焊料熔化。 在预定时间段结束之后，扩散的铜和来自液态焊料的锡形成包含金属间铜 - 锡相的连接层，该连接层的至少90％是由焊料层形成的连接层。

公开(公告)号：US20130277813A1

公开(公告)日：2013-10-24

申请号：US13454115

申请日：2012-04-24

申请人： Holger Torwesten ,  Manfred Mengel ,  Stefan Schmid ,  Soon Lock Goh ,  Swee Kah Lee

发明人： Holger Torwesten ,  Manfred Mengel ,  Stefan Schmid ,  Soon Lock Goh ,  Swee Kah Lee

IPC分类号： H01L23/495 ,  H01L21/50

CPC分类号： H01L23/3121 ,  H01L23/296 ,  H01L23/3142 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48609 ,  H01L2224/48611 ,  H01L2224/48639 ,  H01L2224/48709 ,  H01L2224/48711 ,  H01L2224/48739 ,  H01L2224/48809 ,  H01L2224/48811 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83411 ,  H01L2224/83439 ,  H01L2224/83805 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2224/85409 ,  H01L2224/85411 ,  H01L2224/85439 ,  H01L2224/85805 ,  H01L2224/8592 ,  H01L2224/85939 ,  H01L2924/00011 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01028 ,  H01L2924/01082 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2224/83205

摘要： Embodiments provide a method of forming a chip package. The method may include attaching at least one chip on a carrier, the chip including a plurality of chip pads on a surface of the chip opposite to the carrier; depositing a first adhesion layer on the carrier and on the chip pads of the chip, the first adhesion layer including tin or indium; depositing a second adhesion layer on the first adhesion layer, the second adhesion layer including a silane organic material; and depositing a lamination layer or an encapsulation layer on the second adhesion layer and the chip.

摘要翻译： 实施例提供了形成芯片封装的方法。 该方法可以包括在载体上附加至少一个芯片，该芯片包括在芯片的与载体相对的表面上的多个芯片焊盘; 在所述载体上和所述芯片的所述芯片焊盘上沉积第一粘合层，所述第一粘附层包括锡或铟; 在第一粘合层上沉积第二粘合层，第二粘合层包括硅烷有机材料; 以及在所述第二粘合层和所述芯片上沉积层压层或封装层。