公开(公告)号：US4636832A

公开(公告)日：1987-01-13

申请号：US837663

申请日：1986-03-04

申请人： Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L23/532 ,  H01L23/14

CPC分类号： H01L24/85 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12036 ,  H01L2924/19043 ,  H01L2924/20752

摘要： A semiconductor device with a bonding section comprising a semiconductor substrate, a silicon layer formed on the semiconductor substrate with a first insulating layer interposed therebetween, and a bonding pad formed on the silicon layer with a second insulating layer interposed therebetween. The silicon layer has substantially the same size as the bonding pad. When a lead line is bonded to the bonding pad, the silicon layer lessens the stress caused by the bonding.

摘要翻译： 一种具有接合部分的半导体器件，包括半导体衬底，在半导体衬底上形成有第一绝缘层的硅层，以及形成在硅层上并具有介于其间的第二绝缘层的接合焊盘。 硅层具有与焊盘大致相同的尺寸。 当引线与接合焊盘接合时，硅层减小由接合引起的应力。

公开(公告)号：US4728627A

公开(公告)日：1988-03-01

申请号：US870117

申请日：1986-06-03

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/00 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L21/76885 ,  H01L21/76877 ,  Y10S438/937

摘要： A method of manufacturing a semiconductor device comprising the steps of preparing a semiconductor substrate on which a first insulation film is formed, forming a first conductive layer on the first insulation film, forming a hillock of the first conductive layer, forming a second insulation film on the structure, removing that portion of the second insulation film, in self-align with the hillock, which is on the hillock, thereby forming a contact hole leading to the first conductive layer, and forming on the structure a second conductive layer extending into the contact hole and contacting the first conductive layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备其上形成有第一绝缘膜的半导体衬底，在第一绝缘膜上形成第一导电层，形成第一导电层的小丘，在第一绝缘膜上形成第二绝缘膜 所述结构将所述第二绝缘膜的所述部分与所述小丘上的小丘自对准，从而形成通向所述第一导电层的接触孔，并且在所述结构上形成延伸到所述第一导电层的第二导电层 接触孔并与第一导电层接触。

公开(公告)号：US4613888A

公开(公告)日：1986-09-23

申请号：US634030

申请日：1984-07-24

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

IPC分类号： H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L23/532 ,  H01L21/44 ,  H01L21/47 ,  H01L21/94

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A semiconductor device is disclosed which includes a multilayer formed of a hard inorganic main insulation film and a soft subinsulation film as insulation interlayers, and a hard inorganic insulation film as a final passivation film. The final passivation film is directly deposited on the hard inorganic main insulation film of the multilayer.

摘要翻译： 公开了一种半导体器件，其包括由作为绝缘夹层的硬质无机主绝缘膜和软嵌层膜形成的多层，以及作为最终钝化膜的硬质无机绝缘膜。 最终的钝化膜直接沉积在多层的硬质无机主绝缘膜上。

公开(公告)号：US5175115A

公开(公告)日：1992-12-29

申请号：US654488

申请日：1991-02-13

申请人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

发明人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

IPC分类号： H01L21/48

CPC分类号： H01L21/4846

摘要： Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.

摘要翻译： 进行在Si衬底上形成的Al薄膜的温度 - 内部应力特性的测量。 可以根据测量的特性获得混合在薄膜中的杂质或杂质的量。 当温度升高时获得的特性中，薄膜中Al原子的迁移开始温度作为信息反馈到薄膜形成步骤，从而控制用于形成薄膜的气氛中的杂质量。

公开(公告)号：US4853760A

公开(公告)日：1989-08-01

申请号：US89959

申请日：1987-08-25

申请人： Masahiro Abe ,  Masaharu Aoyama ,  Jiro Ohshima ,  Takashi Ajima

发明人： Masahiro Abe ,  Masaharu Aoyama ,  Jiro Ohshima ,  Takashi Ajima

IPC分类号： H01L21/768 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/312 ,  H01L23/522

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L2924/0002

摘要： A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.

摘要翻译： 半导体器件具有包括聚酰亚胺膜的钝化层。 将氩离子注入到聚酰亚胺膜中以将其转化为电稳定的绝缘膜。

公开(公告)号：US4634496A

公开(公告)日：1987-01-06

申请号：US797986

申请日：1985-11-14

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L21/3205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  B44C1/22 ,  B29C17/08 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/31116 ,  H01L21/31055 ,  H01L21/76819

摘要： A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.

摘要翻译： 一种用于平坦化沉积在第一互连层上的绝缘层的表面以允许沉积在其上的第二互连层而不引起第二互连层的破损的方法。 该方法的特征在于，首先在第一互连层上形成至少两个彼此不同的蚀刻特性的绝缘膜，然后在第二绝缘膜上沉积抗蚀剂层。 随后，蚀刻抗蚀剂层的一部分以暴露第二绝缘膜的顶表面，并且使用剩余的抗蚀剂层作为掩模来选择性地和各向异性地蚀刻第二绝缘膜。 在去除第一绝缘膜和剩余的抗蚀剂标记之后，沉积第三绝缘膜至足以使其表面平坦的厚度。

公开(公告)号：US4520041A

公开(公告)日：1985-05-28

申请号：US548440

申请日：1983-11-03

申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/3205 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532 ,  H01L21/283 ,  H01L21/302

CPC分类号： H01L23/53295 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002

摘要： A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.

摘要翻译： 通过在衬底上形成第一绝缘层和第二绝缘层，可以在半导体衬底上形成具有基本平坦表面的金属化结构。 选择性地去除第二绝缘层以在其中形成凹槽。 然后，顺应地形成金属材料层。 金属层具有与第二绝缘层的槽对应的槽。 将可流动的聚合物施加到所得结构的表面以形成具有平坦表面的层。 依次离子蚀刻聚合物层和金属层以露出第二绝缘层。 因此，由剩余的金属层和第二绝缘层构成的金属化结构形成为具有平坦的表面。

公开(公告)号：US5266526A

公开(公告)日：1993-11-30

申请号：US854812

申请日：1992-03-19

申请人： Masaharu Aoyama ,  Masahiro Abe

发明人： Masaharu Aoyama ,  Masahiro Abe

IPC分类号： H01L21/3205 ,  H01L21/288 ,  H01L21/74 ,  H01L21/768 ,  H01L23/52 ,  H01L21/441 ,  H01L21/469

CPC分类号： H01L21/7688 ,  H01L21/743 ,  Y10S148/10

摘要： A method of forming a trench buried wiring on a semiconductor device. The method includes the steps of: forming a trench in a first insulating film formed on a semiconductor substrate, by using as a mask a photoresist layer, the trench having substantially an upright step; depositing a first electrode material on the surface of the photoresist layer and on the bottom of the trench, while leaving the photoresist layer; removing the photoresist layer and the first electrode material on the photoresist layer while leaving the first electrode material only on the bottom of the trench; and filling a second electrode material in the trench to form a composite electrode with the second electrode material being superposed on the first electrode material.

摘要翻译： 一种在半导体器件上形成沟槽埋入布线的方法。 该方法包括以下步骤：在形成在半导体衬底上的第一绝缘膜中形成沟槽，通过使用光刻胶层作为掩模，该沟槽具有基本上直立的步骤; 在光致抗蚀剂层的表面上和沟槽的底部上沉积第一电极材料，同时留下光致抗蚀剂层; 在光致抗蚀剂层上除去光致抗蚀剂层和第一电极材料，同时仅在沟槽的底部留下第一电极材料; 以及在沟槽中填充第二电极材料以形成复合电极，其中第二电极材料叠置在第一电极材料上。

公开(公告)号：US4717682A

公开(公告)日：1988-01-05

申请号：US830928

申请日：1986-02-19

申请人： Shin-ichi Taka ,  Jiro Ohshima ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Shin-ichi Taka ,  Jiro Ohshima ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/283

CPC分类号： H01L21/743

摘要： A method of manufacturing a semiconductor device, comprising the steps of sequentially forming a buried region and an epitaxial layer on a major surface of a semiconductor substrate, forming a conductive layer along an annular trench extending to the buried region, filling the annular trench with an insulating material and forming a functional element in said epitaxial layer surrounded by said buried region and said insulating material within said annular trench. In this method, the step of forming the conductive layer along the annular trench is carried out by the steps of forming an annular trench extending through said buried region, and depositing a conductive layer on only a side wall surface of said annular trench.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：在半导体衬底的主表面上依次形成掩埋区域和外延层，沿着延伸到掩埋区域的环形沟槽形成导电层，用环形沟槽填充 绝缘材料，并在由所述掩埋区域围绕的所述外延层中形成功能元件，并在所述环形沟槽内形成所述绝缘材料。 在该方法中，沿着环形沟槽形成导电层的步骤是通过形成延伸穿过所述掩埋区域的环形沟槽以及仅在所述环形沟槽的侧壁表面上沉积导电层的步骤来执行的。

公开(公告)号：US4618878A

公开(公告)日：1986-10-21

申请号：US621086

申请日：1984-06-15

申请人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

发明人： Masaharu Aoyama ,  Masahiro Abe ,  Takashi Ajima ,  Toshio Yonezawa

IPC分类号： H01L21/768 ,  H01L21/31 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.

摘要翻译： 一种具有多层布线结构的半导体器件，包括半导体衬底，沉积在所述衬底上的第一布线层和沉积在所述第一布线层上的绝缘层的第二布线层，其中绝缘中间层由无机绝缘层 以及覆盖无机绝缘层的聚酰亚胺系树脂膜。 聚酰亚胺系树脂膜与无机绝缘膜的厚度比为0.1〜0.5。 一种制造多层布线结构的半导体器件的方法，其中在绝缘中间层中形成具有小台阶的开口。