Abstract:
A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer.
Abstract:
A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer.
Abstract:
A power device with improved reliability and a method for producing the same is disclosed. One embodiment provides an active area having an electrical power dissipation characteristic, a metallization layer portion configured with respect to the active area so that the dissipation characteristic of the active area results in heating the metallization layer portion, the metallization layer portion being formed as a connected region. The metallization layer portion has at least one hole, fully extending through the metal layer and having a dielectric. The at least one hole is arranged so that each location of the metal layer portion is connected electrically to each other location via the metallization material of the metal layer portion.
Abstract:
A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer.
Abstract:
A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region. wherein the active region is interrupted by an inactive region, wherein an electrical power dissipation in the inactive region is zero or smaller than an electrical power dissipation in the active region; and a metallization layer arranged with respect to the active region on a surface of the semiconductor device and at least partly overlapping the active area, wherein the metallization layer is divided into a first part, in electrical contact to the first terminal region, and a second part, in electrical contact to the second terminal region, wherein the first and the second part are separated by a gap; and wherein the gap and the inactive region are mutually arranged so that an electrical power dissipation below the gap is reduced compared to an electrical power dissipation below the first part and the second part of the metallization layer.
Abstract:
A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.
Abstract:
Cylindrical optical components of quartz glass are known, which have an inner zone made of an inner zone glass, which extends in the direction of the longitudinal axis and is surrounded by a jacket zone made of a jacket zone glass, the average wall thickness thereof varying at least over a part of its length in the direction of the longitudinal axis of the component. The aim of the invention is to provide a method that allows a simple and cost-effective production of such an optical component from quartz glass. A method is proposed according to the invention, comprising the following method steps: (a) providing a first parison made of an inner zone glass, which has a first contact surface on the end face, said contact surface having a conical external contour; (b) providing a second parison from the jacket zone glass; (c) embedding the contact surface with a conical external contour into the jacket zone glass and welding the contact surface to the jacket zone glass, thereby forming a composite parison which has a cone-shaped inner zone area of inner zone glass in a contact area, said inner zone area being surrounded by a jacket zone area having the shape of an inner cone; and (d) elongation of the composite parison to form the optical component or a preproduct of the component.
Abstract:
An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.
Abstract:
An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.
Abstract:
A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.