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107 条记录 (耗时 0.028 秒)

    Tin deposition
    1.
    发明授权
    Tin deposition 有权
    锡沉积

    公开(公告)号：US07314543B2

    公开(公告)日：2008-01-01

    申请号：US10685659

    申请日：2003-10-14

    申请人： Ming Fang ,  Valery M. Dubin ,  Scott M. Haight

    发明人： Ming Fang ,  Valery M. Dubin ,  Scott M. Haight

    IPC分类号： C25D5/02 ,  C25D7/12 ,  C25D3/30 ,  C25D3/32

    CPC分类号： H01L24/11 ,  C25D3/32 ,  C25D5/02 ,  H01L21/2885 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/00

    摘要： A device includes an integrated circuit and a deposited tin in electrical contact with a portion of the integrated circuit. The deposited tin is formed by electrodeposition from a bath. The deposited tin includes a residue characteristic of the bath. The bath includes a bath-soluble tin compound, a strong acid, and a sulfopropylated anionic surfactant. In another aspect, a composition includes between approximately 20 and 40 grams per liter of one of stannous methane sulfonate, stannous sulfate, and a mixture thereof, between approximately 100 and 200 grams per liter of one of methanesulfonic acid, sulfuric acid, and a mixture thereof, and between approximately 1 and 2 grams per liter of one or more polyethyleneglycol alkyl-3-sulfopropyl diethers. In another aspect, a method includes electroplating tin with a current density of greater than approximately 30 mA/cm2 and a plating efficiency of greater than approximately 95%.

    摘要翻译： 一种器件包括集成电路和与集成电路的一部分电接触的沉积锡。 沉积的锡通过从浴中电沉积形成。 沉积的锡包括浴的特征残留物。 该浴包括溶于水的锡化合物，强酸和磺基丙基化阴离子表面活性剂。 在另一方面，组合物包括约20至40克/升的亚磺酸甲酯磺酸盐，硫酸亚锡及其混合物之间，约100至200克/升甲磺酸，硫酸和混合物之一 和约1至2克/升一种或多种聚乙二醇烷基-3-磺丙基二醚之间。 另一方面，一种方法包括电镀锡，其电流密度大于约30mA / cm 2，电镀效率大于约95％。

    Polymer memory with adhesion layer containing an immobilized metal
    6.
    发明授权
    Polymer memory with adhesion layer containing an immobilized metal 有权
    含有固定金属的粘合层的聚合物记忆

    公开(公告)号：US07709873B2

    公开(公告)日：2010-05-04

    申请号：US11096389

    申请日：2005-03-31

    申请人： Valery M. Dubin ,  Ebrahim Andideh

    发明人： Valery M. Dubin ,  Ebrahim Andideh

    IPC分类号： H01L29/76 ,  H01L29/74 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/10 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/516 ,  H01L29/78391 ,  Y10T29/435

    摘要： An embodiment mitigates one or more of the limiting factors of fabricating polymer ferroelectric memory devices. For example, an embodiment reduces the degradation of the ferroelectric polymer due to the polymer's reaction with, and migration or diffusion of, adjacent metal electrode material. Further, the ferroelectric polymer is exposed to fewer potentially high temperature or high energy processes that may damage the polymer. An embodiment further incorporates an immobilized catalyst to improve the adhesion between adjacent layers, and particularly between the electrolessly plated electrodes and the ferroelectric polymer.

    摘要翻译： 一个实施例减轻了制造聚合物铁电存储器件的一个或多个限制因素。 例如，一个实施方案由于聚合物与相邻的金属电极材料的反应和迁移或扩散而降低了铁电聚合物的劣化。 此外，铁电聚合物暴露于可能损坏聚合物的较少的潜在高温或高能量过程。 一个实施方案还包括固定化的催化剂以改善相邻层之间的粘合性，特别是在无电镀电极和铁电聚合物之间。

    CARBON NANOTUBE INTERCONNECT STRUCTURES
    7.
    发明申请
    CARBON NANOTUBE INTERCONNECT STRUCTURES 审中-公开
    碳纳米管互连结构

    公开(公告)号：US20100022083A1

    公开(公告)日：2010-01-28

    申请号：US12548779

    申请日：2009-08-27

    申请人： Florian Gstrein ,  Valery M. Dubin ,  Juan E. Dominguez ,  Adrien R. Lavoie

    发明人： Florian Gstrein ,  Valery M. Dubin ,  Juan E. Dominguez ,  Adrien R. Lavoie

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/76838 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/75 ,  H01L2924/00

    摘要： A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles.

    摘要翻译： 一种包括在牺牲衬底上形成单层碳纳米管的互连的方法; 将所述互连件从所述牺牲衬底转移到电路衬底; 以及将所述互连件耦合到所述电路基板上的接触点。 一种方法，包括在第一接触点和第二接触点之间的电路基板上形成纳米管束，所述纳米管限定通过其的腔; 用导电材料填充纳米管束管腔长度的一部分; 以及将所述导电材料耦合到所述第二接触点。 一种包括计算设备的系统，包括微处理器，微处理器耦合到印刷电路板，微处理器包括具有多个电路器件的衬底，该电路器件具有通过包括碳纳米管束的互连结构与多个电路器件形成的电连接。

    Copper nucleation in interconnects having ruthenium layers
    8.
    发明申请
    Copper nucleation in interconnects having ruthenium layers 审中-公开
    具有钌层的互连中的铜成核

    公开(公告)号：US20080296768A1

    公开(公告)日：2008-12-04

    申请号：US11639636

    申请日：2006-12-14

    申请人： Ramanan V. Chebiam ,  Valery M. Dubin

    发明人： Ramanan V. Chebiam ,  Valery M. Dubin

    IPC分类号： H01L29/40 ,  H01L21/44

    CPC分类号： H01L21/76873 ,  H01L21/76846 ,  H01L21/76864 ,  H01L2221/1089

    摘要： A method for fabrication a metal interconnect that includes a ruthenium layer and minimizes void formation comprises forming a barrier layer on a substrate having a trench, depositing a ruthenium layer on the barrier layer, depositing an alloy-seed layer on the ruthenium layer, using an electroless plating process to deposit a copper seed layer on the alloy-seed layer, and using an electroplating process to deposit a bulk metal layer on the copper seed layer. The alloy-seed layer inhibits void formation issues at the ruthenium-copper interface and improves electromigration issues. The electroless copper seed layer inhibits the alloy-seed layer from dissolving into the electroplating bath and reduces electrical resistance across the substrate during the electroplating process.

    摘要翻译： 一种用于制造包括钌层并且使空隙形成最小化的金属互连的方法包括在具有沟槽的衬底上形成阻挡层，在阻挡层上沉积钌层，在钌层上沉积合金种子层，使用 化学镀处理以在合金种子层上沉积铜籽晶层，并使用电镀工艺在铜籽晶层上沉积体金属层。 合金种子层抑制钌 - 铜界面处的空隙形成问题，并改善电迁移问题。 化学镀铜种子层抑制合金种子层溶解到电镀浴中，并且在电镀过程期间降低跨衬底的电阻。