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21 条记录 (耗时 0.025 秒)

    Capacitor structure for an integrated circuit
    6.
    发明授权
    Capacitor structure for an integrated circuit 失效
    集成电路的电容结构

    公开(公告)号：US5583359A

    公开(公告)日：1996-12-10

    申请号：US398264

    申请日：1995-03-03

    申请人： Anthony C. C. Ng ,  Mukul Saran

    发明人： Anthony C. C. Ng ,  Mukul Saran

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/92 ,  H01L27/108

    CPC分类号： H01L23/5223 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002

    摘要： A capacitor structure for an integrated circuit and a method of fabrication are described. The capacitor structure is defined by layers forming interconnect metallization and interlayer dielectrics. The latter are relatively thick, and provide high breakdown voltages. Multilevel metallization schemes allow for a stack of a plurality of electrodes to be provided. The electrodes may take the form of stacks of flat plates interconnected in parallel so that the capacitance is the sum of capacitances of alternate layers in the stack. Advantageously each electrode comprises a main portion and a surrounding portion having the form of a protecting ring, coplanar with the main portion of the electrode. The ring prevents thinning of the dielectric near edges of electrode during fabrication, to improve control of breakdown voltages for high voltage applications. Alternative electrode structures employing a plurality of interconnected fingers, and particularly a configuration having interdigitated fingers, are provided to increase the capacitance per unit surface area. Parallel electrode fingers are stacked in vertical alignment, or offset, and interconnected to provide vertical, horizontal or inclined stacks having different patterns of polarities, thereby forming capacitors of various configurations. The capacitor structures have particular application for high voltage (>100 V), low leakage and high frequency (MHz/GHz) applications.

    摘要翻译： 描述了用于集成电路的电容器结构和制造方法。 电容器结构由形成互连金属化和层间电介质的层限定。 后者相对较厚，并提供高击穿电压。 多层金属化方案允许提供多个电极的堆叠。 电极可以采取并联互连的平板堆叠的形式，使得电容是叠层中交替层的电容之和。 有利地，每个电极包括具有与电极的主要部分共面的保护环形式的主要部分和环绕部分。 环在制造期间防止电极边缘附近的电介质变薄，以改善对高压应用的击穿电压的控制。 提供采用多个互连指状物的替代电极结构，特别是具有交叉指状物的构​​造，以增加每单位表面积的电容。 平行电极指以垂直对准或偏移方式堆叠并互连以提供具有不同图案极性的垂直，水平或倾斜堆叠，由此形成各种构造的电容器。 电容器结构具有高电压（> 100 V），低漏电和高频（MHz / GHz）应用的特殊应用。

    High capacitance damascene capacitors
    9.
    发明授权
    High capacitance damascene capacitors 有权

    公开(公告)号：US06617208B2

    公开(公告)日：2003-09-09

    申请号：US09932400

    申请日：2001-08-17

    申请人： Mukul Saran

    发明人： Mukul Saran

    IPC分类号： H01L48242

    CPC分类号： H01L21/76808 ,  H01L28/40 ,  H01L28/82 ,  H01L28/87

    摘要： The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer 60 is sandwiched between two conductive plates 40 and 75 to form an integrated circuit capacitor. One metal plate 40 is copper formed using a damascene process. The high capacitance of the structure is due to the thin high k dielectric material used to form the etch-stop/capacitor dielectric layer 60.

    Method for reducing via resistance in small high aspect ratio holes filled using aluminum extrusion
    10.
    发明授权
    Method for reducing via resistance in small high aspect ratio holes filled using aluminum extrusion 有权
    使用铝挤压填充的小型高纵横比孔中减小通孔电阻的方法

    公开(公告)号：US06189209B1

    公开(公告)日：2001-02-20

    申请号：US09179919

    申请日：1998-10-27

    申请人： Mukul Saran

    发明人： Mukul Saran

    IPC分类号： H01K310

    CPC分类号： H01L23/53223 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S439/931 ,  Y10T29/49165 ,  H01L2924/00

    摘要： A method of forming an electrical interconnect through a via to electrically couple two electrically conductive layers and the device. There are provided a pair of electrically conductive layers and an electrically insulating layer between the pair of electrically conductive layers having a via extending between the pair of electrically conductive layers. A layer of titanium is formed covering the walls of the via and extending onto one of the pair of electrically conductive layers. A thin layer of titanium nitride with a poor step ?? technique is formed covering the titanium on the walls but not covering the titanium on the one of the pair of electrically conductive layers. The remainder of the via is filled with aluminum. The layer of titanium and the layer of titanium nitride preferably extend out of the via and between the electrically insulating layer and at least one of the pair of electrically conductive layers. The aluminum is substantially everywhere spaced from the portion of the layer of titanium covering the walls of the via. The filling of the remainder of the via with aluminum can include deposition of aluminum in the via, heating the aluminum to a temperature at which it is plastically deformable and applying pressure to the aluminum to cause the aluminum to substantially fill voids within the aluminum.

    摘要翻译： 通过通孔形成电互连以电耦合两个导电层和该器件的方法。 在一对导电层之间设置有一对导电层和电绝缘层，该导电层具有在一对导电层之间延伸的通孔。 形成覆盖通孔的壁并延伸到一对导电层中的一层的钛层。 一薄层氮化钛，步骤差？ 形成了在壁上覆盖钛而不覆盖一对导电层之一上的钛的技术。 通孔的其余部分填充有铝。 钛层和氮化钛层优选延伸出通孔，并且在电绝缘层和一对导电层中的至少一个之间延伸。 铝层几乎与覆盖通孔壁的钛层的部分隔开。 用铝填充剩余的通孔可以包括在通孔中沉积铝，将铝加热至其可塑性变形的温度，并向铝施加压力以使铝基本上填充铝内的空隙。