公开(公告)号：US20230369179A1

公开(公告)日：2023-11-16

申请号：US18172665

申请日：2023-02-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsuhiko KITAGAWA ,  Takehiko MAEDA ,  Kuniharu MUTO ,  Takeshi MIYAKOSHI

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L23/49582 ,  H01L23/3121 ,  H01L21/565 ,  H01L24/48 ,  H01L24/05 ,  H01L2224/04042 ,  H01L2224/48247 ,  H01L2924/35121 ,  H01L2924/181

Abstract: A semiconductor device includes: a die pad having an upper surface facing a semiconductor chip, a metal film formed on the upper surface, and a bonding material formed so as to cover the metal film. Here, the upper surface has: a first region overlapping the semiconductor chip, a second region not overlapping the semiconductor chip, a third region included in the first region and covered with the metal film, and a fourth region included in the first region and adjacent to the third region and also not covered with the metal film. Also, the semiconductor chip is mounted on the die pad such that a center of the semiconductor chip overlaps the third region. Further, an area of the third region is greater than or equal to 11% of an area of the first region, and less than or equal to 55% of the area of the first region.

公开(公告)号：US20170033710A1

公开(公告)日：2017-02-02

申请号：US15194624

申请日：2016-06-28

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Koji BANDO ,  Takamitsu KANAZAWA ,  Ryo KANDA ,  Akihiro TAMURA ,  Hirobumi MINEGISHI

IPC: H02M7/537 ,  H03K17/567 ,  H01L23/495 ,  H01L23/04 ,  H01L27/06 ,  H02M7/00

CPC classification number: H02M7/537 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/49541 ,  H01L27/0664 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H02M7/003 ,  H02M7/53875 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

Abstract translation: 提高了半导体器件的可靠性。 其上形成有控制电路的第三半导体芯片，并且多个IGBT芯片的第一半导体芯片经由高侧继电器板电连接。 也就是说，第一半导体芯片和第三半导体芯片经由第一线，高侧继电器板和第二线电连接。 类似地，其上形成有控制电路的第三半导体芯片和多个IGBT芯片的第二半导体芯片经由低侧继电器板电连接。 也就是说，第二半导体芯片和第三半导体芯片经由第一线，低侧继电器板和第二线电连接。

公开(公告)号：US20190035745A1

公开(公告)日：2019-01-31

申请号：US16151585

申请日：2018-10-04

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Ryo KANDA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L23/495 ,  H01L23/544 ,  H02M7/5387 ,  H02M7/00 ,  H02P27/06 ,  H02M1/00

Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

公开(公告)号：US20190378785A1

公开(公告)日：2019-12-12

申请号：US16410768

申请日：2019-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kuniharu MUTO ,  Hideyuki NISHIKAWA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00 ,  H01L23/544

Abstract: Assembly of the semiconductor device includes the following steps: (a) mounting a semiconductor chip on the bottom electrode 40; (b) mounting the top electrode 30 on the semiconductor chip; (c) forming a sealing body 70 made of resin and provided with a convex portion 74 so as to cover the semiconductor chip; and (d) exposing the electrode surface 31 of the top electrode 30 on the top surface of the sealing body 70 and exposing the electrode surface 41 of the bottom electrode 40 on the back surface of the sealing body 70. In the step (d), at least one of the electrode surface 31 and the electrode surface 41 is exposed from the sealing body 70 by irradiating at least one of the front surface and the back surface of the sealing body 70 with the laser 110.

公开(公告)号：US20190006258A1

公开(公告)日：2019-01-03

申请号：US15969897

申请日：2018-05-03

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Koji BANDO

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L25/16 ,  H01L25/00 ,  H01L21/48 ,  H01L23/40 ,  H01L23/00

Abstract: Reliability of a semiconductor module is improved. In a resin mold step of assembly of a semiconductor module, an IGBT chip, a diode chip, a control chip, a part of each of chip mounting portions are resin molded so that a back surface of each of the chip mounting portions is exposed from a back surface of a sealing body. After the resin molding, an insulating layer is bonded to the back surface of the sealing body so as to cover each back surface (exposed portion) of the chip mounting portions, and then, a TIM layer is bonded to an insulating layer. Here, a region of the TIM layer in a plan view is included in a region of the insulating layer.

公开(公告)号：US20180241319A1

公开(公告)日：2018-08-23

申请号：US15891872

申请日：2018-02-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji BANDO ,  Kuniharu MUTO ,  Hideaki SATO

IPC: H02M7/48 ,  H02M7/00 ,  H01L23/12 ,  H01L25/16 ,  H01L25/18 ,  H03K17/64

CPC classification number: H02M7/48 ,  H01L23/12 ,  H01L23/3735 ,  H01L25/16 ,  H01L25/18 ,  H02M7/003 ,  H03K17/64

Abstract: An electronic device includes a first substrate, a wiring substrate (second substrate) disposed over the first substrate, and an enclosure (case) in which the first substrate and the wiring substrate are accommodated and that has a first side and a second side. A driver component (semiconductor component) is mounted on the wiring substrate. A gate electrode of a first semiconductor component is electrically connected to the driver component via a lead disposed on a side of the first side and a wiring disposed between the driver component and the first side. A gate electrode of a second semiconductor component is electrically connected to the driver component via a lead disposed on a side of the second side and a wiring disposed between the driver component and the second side.

公开(公告)号：US20180182719A1

公开(公告)日：2018-06-28

申请号：US15833289

申请日：2017-12-06

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Ryo KANDA

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H02M7/5387

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/495 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/48 ,  H01L2223/54486 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48155 ,  H01L2224/48245 ,  H01L2224/4903 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/14252 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H02M7/003 ,  H02M7/5387 ,  H02M2001/0009 ,  H02P27/06

Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

公开(公告)号：US20180138828A1

公开(公告)日：2018-05-17

申请号：US15867978

申请日：2018-01-11

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Koji BANDO ,  Takamitsu KANAZAWA ,  Ryo KANDA ,  Akihiro TAMURA ,  Hirobumi MINEGISHI

IPC: H02M7/537 ,  H01L23/04 ,  H02M7/00 ,  H01L27/06

CPC classification number: H02M7/537 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/49541 ,  H01L27/0664 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H02M7/003 ,  H02M7/53875 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

公开(公告)号：US20130207252A1

公开(公告)日：2013-08-15

申请号：US13846730

申请日：2013-03-18

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu MUTO ,  Toshiyuki HATA ,  Hiroshi SATO ,  Hiroi OKA ,  Osamu IKEDA

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L23/49503 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/544 ,  H01L24/05 ,  H01L24/29 ,  H01L24/35 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/77 ,  H01L24/78 ,  H01L24/83 ,  H01L24/84 ,  H01L24/85 ,  H01L29/0615 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2223/54406 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49111 ,  H01L2224/4912 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84205 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85214 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/83205 ,  H01L2924/206

Abstract: To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Abstract translation: 实现密封在其中的功率MOSFET的小型表面安装封装的导通电阻的降低。 硅芯片安装在与构成漏极引线的引线集成的管芯焊盘部分上。 硅芯片在其主表面上具有源极焊盘和栅极焊盘。 硅芯片的背面配置功率MOSFET的漏极，并通过Ag浆料粘合到芯片焊盘部分的上表面。 构成源极引线的引线通过Al带电耦合到源极焊盘，而构成栅极引线的引线通过Au线电耦合到栅极焊盘。