公开(公告)号：US20130033827A1

公开(公告)日：2013-02-07

申请号：US13198756

申请日：2011-08-05

申请人： Rabindra N. Das ,  Voya R. Markovich ,  John M. Lauffer ,  Roy H. Magnuson ,  Konstantinos I. Papathomas ,  Benson Chan

发明人： Rabindra N. Das ,  Voya R. Markovich ,  John M. Lauffer ,  Roy H. Magnuson ,  Konstantinos I. Papathomas ,  Benson Chan

IPC分类号： H05K5/00 ,  H05K1/09 ,  B23K31/02 ,  H05K1/00 ,  H01B1/00 ,  H01B1/02

CPC分类号： H05K1/0313 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/52 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/097 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0257 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0425 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.

摘要翻译： 用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。 具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。 导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。

公开(公告)号：US09451693B2

公开(公告)日：2016-09-20

申请号：US13198756

申请日：2011-08-05

申请人： Rabindra N. Das ,  Voya R. Markovich ,  John M. Lauffer ,  Roy H. Magnuson ,  Konstantinos I. Papathomas ,  Benson Chan

发明人： Rabindra N. Das ,  Voya R. Markovich ,  John M. Lauffer ,  Roy H. Magnuson ,  Konstantinos I. Papathomas ,  Benson Chan

IPC分类号： H05K1/11 ,  H05K1/03

CPC分类号： H05K1/0313 ,  B23K26/382 ,  B23K26/40 ,  B23K2101/40 ,  B23K2103/16 ,  B23K2103/172 ,  B23K2103/52 ,  H01B1/22 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01322 ,  H01L2924/15311 ,  H05K1/097 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0257 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/10378 ,  H05K2203/0425 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

摘要： A multilayer capable electrically conductive adhesive (ECA) mixture for connecting multilevel Z-axis interconnects and a method of forming the ECA for connecting multilevel Z-axis interconnects. The multilayer capable ECA contains a mixture of constituent components that allow the paste to be adapted to specific requirements wherein the method of making a circuitized substrate assembly in which two or more subassemblies having potentially disparate coefficients of thermal expansion (CTE) are aligned and Z-axis interconnection are created during bonding. The metallurgies of the conductors, and those of a multilayer capable conductive paste, are effectively mixed and the flowable interim dielectric used between the mating subassemblies flows to engage and surround the conductor coupling.

摘要翻译： 用于连接多级Z轴互连的多层导电粘合剂（ECA）混合物和形成连接多级Z轴互连的ECA的方法。 具有多层能力的ECA包含允许糊料适应特定要求的组成成分的混合物，其中制造电路化衬底组件的方法，其中具有潜在不同的热膨胀系数（CTE）的两个或更多个子组件对齐，并且Z- 在连接期间创建轴互连。 导体的冶金和多层导电浆料的冶金被有效地混合，并且在配合子组件之间使用的可流动的中间电介质流动以接合和围绕导体耦合。

公开(公告)号：US07442879B2

公开(公告)日：2008-10-28

申请号：US11244180

申请日：2005-10-06

申请人： Rabindra N. Das ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich

发明人： Rabindra N. Das ,  John M. Lauffer ,  Roy H. Magnuson ,  Voya R. Markovich

IPC分类号： H01R12/04 ,  H05K1/11

CPC分类号： H05K3/4069 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/015 ,  H05K2201/0245 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/1152

摘要： A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a binder component and at least one metallic component including microparticles. In another embodiment, the paste includes the binder and a plurality of nano-wires. Selected ones of the microparticles or nano-wires include a layer of solder thereon. A method of making such a substrate is also provided, as are an electrical assembly and information handling system adapter for having such a substrate as part thereof.

摘要翻译： 一种电路化基板，包括用于提供电连接的导电浆料。 在一个实施方案中，糊状物包含粘合剂组分和至少一种包含微粒的金属组分。 在另一个实施方案中，糊状物包括粘合剂和多根纳米线。 所选择的微粒或纳米线包括其上的焊料层。 还提供了制造这种基板的方法，以及用于将这种基板作为其一部分的电组件和信息处理系统适配器。

公开(公告)号：US08685284B2

公开(公告)日：2014-04-01

申请号：US12884657

申请日：2010-09-17

申请人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

IPC分类号： H01B1/00 ,  H01B1/22 ,  H01B1/02

CPC分类号： H01B1/22 ,  H01L2224/81 ,  Y10T29/49117

摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

摘要翻译： 导电糊和形成用于器件级互连的糊的方法。 导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。 通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。 一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。 通常，小于5微米的平均片尺寸适用于五微米互连。 然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。 最终混合物中基于LMP的糊剂的量优选为20-50重量％。 纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

公开(公告)号：US20120069531A1

公开(公告)日：2012-03-22

申请号：US12884657

申请日：2010-09-17

申请人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Roy H. Magnuson ,  Mark D. Poliks ,  Voya R. Markovich

IPC分类号： H05K7/00 ,  H01B1/02 ,  H01B1/22 ,  H01R43/00

CPC分类号： H01B1/22 ,  H01L2224/81 ,  Y10T29/49117

摘要： A conducting paste and method of forming the paste for device level interconnection. The conducting paste contains metal loading in the range 80-95% that is useful for making five micron device level interconnects. The conducting paste is made by mixing two different conducting pastes, each paste maintaining its micro level individual rich region in the mixed paste even after final curing. One paste contains at least one low melting point alloy and the other paste contains noble metal fillers such as gold or silver flakes. In general, average flake size below five micron is suitable for five micron interconnects. However, 1 micron or smaller silver flakes and an LMP mixture is preferred for five micron interconnects. The amount of LMP based paste in the final mixture is preferably 20-50% by weight. The nano micro paste embodiment shows good electrical yield (81%) and low contact resistance.

摘要翻译： 导电糊和形成用于器件级互连的糊的方法。 导电浆料含有80-95％范围内的金属负载，可用于制造五微米器件级互连。 通过混合两种不同的导电浆料制成导电糊料，即使在最终固化后，每个糊料仍将其微量级独立富含区域保持在混合糊料中。 一种糊状物含有至少一种低熔点合金，另一种糊状物含有贵金属填料如金或银薄片。 通常，小于5微米的平均片尺寸适用于五微米互连。 然而，对于5微米互连，优选1微米或更小的银薄片和LMP混合物。 最终混合物中基于LMP的糊剂的量优选为20-50重量％。 纳米微膏实施例显示良好的电收率（81％）和低接触电阻。

公开(公告)号：US07897877B2

公开(公告)日：2011-03-01

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H05K1/16

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US20110043987A1

公开(公告)日：2011-02-24

申请号：US12938759

申请日：2010-11-03

申请人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich

发明人： Rabindra N. Das ,  John M. Lauffer ,  Voya R. Markovich

IPC分类号： G06F1/16 ,  H05K7/00 ,  B82Y30/00

CPC分类号： H05K1/167 ,  H01G4/206 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/095 ,  H05K1/162 ,  H05K3/0023 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0215 ,  H05K2201/0257 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49087 ,  Y10T29/49089 ,  Y10T29/49091 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

摘要： A method of making a circuitized substrate including a resistor comprised of material which includes a polymer resin and a quantity of nano-powders including a mixture of at least one metal component and at least one ceramic component. The ceramic component may be a ferroelectric ceramic and/or a high surface area ceramic and/or a transparent oxide and/or a dope manganite. Alternatively, the material will include the polymer resin and nano-powders, with the nano-powders comprising at least one metal coated ceramic and/or at least one oxide coated metal component. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) utilizing such a circuitized substrate are also provided.

摘要翻译： 一种制造电路化基板的方法，包括由包括聚合物树脂的材料和包括至少一种金属组分和至少一种陶瓷组分的混合物的纳米粉末的量组成的电阻器。 陶瓷部件可以是铁电陶瓷和/或高表面积陶瓷和/或透明氧化物和/或掺杂亚锰酸盐。 或者，材料将包括聚合物树脂和纳米粉末，其中纳米粉末包含至少一种金属涂覆的陶瓷和/或至少一种氧化物涂覆的金属组分。 还提供了使用这种电路化基板的电气组件（基板和至少一个电气部件）以及信息处理系统（例如，个人计算机）。

公开(公告)号：US07449381B2

公开(公告)日：2008-11-11

申请号：US11352279

申请日：2006-02-13

申请人： Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/8234 ,  H01L21/00

CPC分类号： H05K1/162 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/013 ,  H05K2203/0568

摘要： A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.

摘要翻译： 一种形成电容衬底的方法，其中材料的至少一个电容介电层被屏幕或喷墨印刷到导体上，然后进一步处理衬底，包括添加通孔以将所选择的元件耦合到衬底内以形成 至少两个电容器作为衬底的内部元件。 电容性衬底可以结合在更大的电路化衬底内，例如以形成电组件。 还提供了一种制造包括这种基板的信息处理系统的方法。

公开(公告)号：US07429510B2

公开(公告)日：2008-09-30

申请号：US11352276

申请日：2006-02-13

申请人： Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/8242 ,  H05K1/16

CPC分类号： H05K1/162 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2203/0568

摘要： A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. Photoimageable material is used to facilitate positioning of the capacitive dielectric being printed. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.

摘要翻译： 一种形成电容衬底的方法，其中材料的至少一个电容介电层被屏幕或喷墨印刷到导体上，然后进一步处理衬底，包括添加通孔以将所选择的元件耦合到衬底内以形成 至少两个电容器作为衬底的内部元件。 可光成像材料用于促进正在印刷的电容电介质的定位。 电容性衬底可以结合在更大的电路化衬底内，例如以形成电组件。 还提供了一种制造包括这种基板的信息处理系统的方法。

公开(公告)号：US20070275525A1

公开(公告)日：2007-11-29

申请号：US11438424

申请日：2006-05-23

申请人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

发明人： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC分类号： H01L21/8242

CPC分类号： H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

摘要： A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

摘要翻译： 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。