公开(公告)号：US5391516A

公开(公告)日：1995-02-21

申请号：US774427

申请日：1991-10-10

申请人： Robert J. Wojnarowski ,  Bernard Gorowitz

发明人： Robert J. Wojnarowski ,  Bernard Gorowitz

IPC分类号： H01L21/768 ,  H01L21/268 ,  H01L21/311 ,  H01L21/441

CPC分类号： H01L21/76877 ,  H01L24/05 ,  H01L2924/12042 ,  H01L2924/14

摘要： Semiconductor device contact pads are enhanced by forming a metal plate over at least a portion of the contact pad. "Enhancement" includes repair such as by bridging a reinforcing pad area over probe damage, general reinforcement or enlargement of a contact pad, and placement of a protective buffer pad over a contact pad. These methods are applicable to any semiconductor device with contact pads on a surface thereof, such as entire wafers, individual dice, and multi-chip High Density Interconnect (HDI) modules. The pad enhancement plate is formed by applying a planarizing dielectric layer over the entire device (if not already formed in the initial stages of HDI processing), and an enhancement access via is then formed to expose a portion of the contact pad to be enhanced. The entire device is metallized, and metal not over the exposed portion of the contact pad is subsequently removed. Localized heating of the metal plate can be achieved by a laser to effectuate a selective pseudo-weld or produce sintering for a low resistance ohmic contact.

摘要翻译： 通过在接触垫的至少一部分上形成金属板来增强半导体器件接触焊盘。 “增强”包括修复，例如通过桥接加强垫区域超过探测器损伤，通常加强或扩大接触垫，以及将保护性缓冲垫放置在接触垫上。 这些方法适用于具有其表面上的接触焊盘的任何半导体器件，例如整个晶片，单个晶片和多芯片高密度互连（HDI）模块。 通过在整个装置（如果在HDI处理的初始阶段尚未形成）中施加平坦化介电层来形成焊盘增强板，然后形成增强接入通路，以使接触焊盘的一部分暴露出增强。 整个装置被金属化，并且随后去除接触垫的暴露部分之上的金属。 可以通过激光来实现金属板的局部加热，以实现选择性伪焊接或产生用于低电阻欧姆接触的烧结。

公开(公告)号：US5527741A

公开(公告)日：1996-06-18

申请号：US321346

申请日：1994-10-11

申请人： Herbert S. Cole ,  Raymond A. Fillion ,  Bernard Gorowitz ,  Ronald F. Kolc ,  Robert J. Wojnarowski

发明人： Herbert S. Cole ,  Raymond A. Fillion ,  Bernard Gorowitz ,  Ronald F. Kolc ,  Robert J. Wojnarowski

IPC分类号： H01L21/60 ,  H01L21/48 ,  H01L23/538 ,  H05K3/32

CPC分类号： H05K3/32 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5387 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  Y10T29/4913

摘要： A method for fabricating a circuit module includes applying an outer insulative layer over a first patterned metallization layer on a first surface of a base insulative layer. A second surface of the base insulative layer has a second patterned metallization layer. At least one circuit chip having chip pads is attached to the second surface of the base insulative layer. Respective vias are formed to expose selected portions of the first patterned metallization layer, the second patterned metallization layer, and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer to extend through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the first and second metallization layers.

摘要翻译： 一种用于制造电路模块的方法包括在绝缘层的第一表面上的第一图案化金属化层上施加外部绝缘层。 基极绝缘层的第二表面具有第二图案化金属化层。 具有芯片焊盘的至少一个电路芯片附接到基极绝缘层的第二表面。 形成各个通孔以暴露第一图案化金属化层，第二图案化金属化层和芯片焊盘的选定部分。 图案化的外部金属化层被施加在外部绝缘层上以延伸通过选定的通孔以互连所选择的芯片焊盘和第一和第二金属化层的选定部分。

公开(公告)号：US5366906A

公开(公告)日：1994-11-22

申请号：US962000

申请日：1992-10-16

申请人： Robert J. Wojnarowski ,  Constantine A. Neugebauer ,  Wolfgang Daum ,  Bernard Gorowitz ,  Eric J. Wildi ,  Michael Gdula ,  Stanton E. Weaver, Jr. ,  Anthony A. Immorlica, Jr.

发明人： Robert J. Wojnarowski ,  Constantine A. Neugebauer ,  Wolfgang Daum ,  Bernard Gorowitz ,  Eric J. Wildi ,  Michael Gdula ,  Stanton E. Weaver, Jr. ,  Anthony A. Immorlica, Jr.

IPC分类号： G01R31/3185 ,  H01L21/301 ,  H01L21/66 ,  H01L23/538 ,  H01L23/58 ,  G01R31/26

CPC分类号： H01L22/22 ,  H01L22/32 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  G01R31/318505 ,  G01R31/318533 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351

摘要： In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

摘要翻译： 在制造晶片级集成互连件时，使用临时或永久的电介质层和电导体图案来提供晶片级整合或测试和老化。 可以使用抗蚀剂来覆盖晶片上的IC焊盘的区域，而去除电导体图案的其余部分以提供晶片级整合结构的修复。 电导体的图案可以被配置为使得在多个晶片上的至少一些子电路之间的导体长度对于信号传播目的而基本上是电相等的; 可以使用粘合剂将另外的晶片层压到晶片上; 受控的曲折可以被切入晶片; 并且晶片可以互连到接口环。

公开(公告)号：US5567657A

公开(公告)日：1996-10-22

申请号：US567386

申请日：1995-12-04

申请人： Robert J. Wojnarowski ,  Thomas B. Gorczyca

发明人： Robert J. Wojnarowski ,  Thomas B. Gorczyca

IPC分类号： H01L23/538 ,  H01L25/065 ,  H05K1/18 ,  H01L21/60

CPC分类号： H01L24/76 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/82 ,  H01L25/0652 ,  H05K1/185 ,  H05K1/186 ,  H01L2224/18 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K2201/10674 ,  H05K3/4611 ,  Y10S438/928

摘要： First and second flexible interconnect structures are provided and each includes a flexible interconnect layer and a chip with a surface having chip pads attached to the flexible interconnect layer. Molding material is inserted between the flexible interconnect layers for encapsulating the respective chips. Vias in the flexible interconnect layers are formed to extend to selected chip pads, and a pattern of electrical conductors is applied which extends over the flexible interconnect layers and into the vias to couple selected ones of the chip pads.

摘要翻译： 提供了第一和第二柔性互连结构，并且每个包括柔性互连层和具有连接到柔性互连层的具有芯片焊盘的表面的芯片。 将成型材料插入在柔性互连层之间以封装相应的芯片。 柔性互连层中的通孔被形成为延伸到选定的芯片焊盘，并且施加电导体图案，该图案在柔性互连层上延伸并穿过通孔以耦合选定的芯片焊盘。

公开(公告)号：US5546654A

公开(公告)日：1996-08-20

申请号：US297076

申请日：1994-08-29

申请人： Robert J. Wojnarowski ,  Thomas B. Gorczyca

发明人： Robert J. Wojnarowski ,  Thomas B. Gorczyca

IPC分类号： H05K1/18 ,  H05K3/28 ,  H05K3/30 ,  B23P19/04 ,  H05K3/42

CPC分类号： H05K3/284 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/15153 ,  H05K1/182 ,  Y10S29/044 ,  Y10T279/11 ,  Y10T29/49146 ,  Y10T29/49165 ,  Y10T29/53191

摘要： A method for fabricating an electronic assembly comprises attaching an insulative film to a frame and positioning at least one electronic component having a face with connections pads face down on the insulative film. The insulative film is positioned on a porous sheet supported by a vacuum fixture. The porous sheet and vacuum fixture are adapted so as to be capable of creating vacuum conditions for holding the insulative film with a substantially flat surface on the porous sheet. A vacuum is created within the vacuum chamber for flatly holding the insulative film on the porous sheet. A substrate is applied to the insulative film and the at least one electronic component. In one embodiment the substrate is applied by securing the insulative film in position with a mold form having at least one opening around the electronic component and adding substrate molding material at least partially around the component through the opening. In another embodiment the substrate is applied by providing a substrate having at least one well therein and positioning the insulative film over at least a portion of the substrate and the electronic component into the well.

摘要翻译： 一种用于制造电子组件的方法包括将绝缘膜附接到框架并且将至少一个具有面的电子部件定位在绝缘膜上，连接焊盘面向下。 绝缘膜位于由真空夹具支撑的多孔片上。 多孔片材和真空固定装置适于能够产生用于将绝缘膜保持在多孔片材上具有基本平坦的表面的真空条件。 在真空室内产生真空，以将绝缘膜平坦地保持在多孔片上。 将衬底施加到绝缘膜和至少一个电子部件。 在一个实施例中，通过用绝缘膜将电绝缘薄膜固定在适当的位置上来施加基底，该模具形式具有围绕电子部件的至少一个开口，并且通过该开口至少部分地围绕该部件添加基底模制材料。 在另一个实施例中，通过提供其中具有至少一个阱的衬底并将绝缘膜定位在衬底和电子部件的至少一部分进入阱中来施加衬底。

公开(公告)号：US5422513A

公开(公告)日：1995-06-06

申请号：US329516

申请日：1993-10-04

申请人： Walter M. Marcinkiewicz ,  Raymond A. Fillion ,  Barry S. Whitmore ,  Robert J. Wojnarowski

发明人： Walter M. Marcinkiewicz ,  Raymond A. Fillion ,  Barry S. Whitmore ,  Robert J. Wojnarowski

IPC分类号： H01L23/538 ,  H01L23/485 ,  H01L29/44 ,  H01L29/52 ,  H01L29/60

CPC分类号： H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/2402 ,  H01L2224/24227 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/3011

摘要： A high density interconnect (HDI) structure having a dielectric multi-layer interconnect structure on a substrate is fabricated by forming a chip well, placing a chip in the well, and connecting the chip to the interconnect structure. Additionally, temperature sensitive chips or devices may be located beneath the dielectric multi-layer interconnect structure. A spacer die may be located in the substrate while the interconnect structure is fabricated and removed after a chip well aligned with the spacer die is formed, in order to accommodate a chip thickness which is greater than the dielectric multi-layer interconnect structure thickness.

摘要翻译： 通过形成芯片，将芯片放置在阱中，并将芯片连接到互连结构来制造在衬底上具有电介质多层互连结构的高密度互连（HDI）结构。 此外，温度敏感的芯片或器件可以位于电介质多层互连结构之下。 间隔管芯可以位于衬底中，同时在形成与间隔管芯形成良好对准的芯片之后制造和移除互连结构，以便适应大于电介质多层互连结构厚度的芯片厚度。

公开(公告)号：US5359496A

公开(公告)日：1994-10-25

申请号：US67157

申请日：1993-05-26

申请人： William P. Kornrumpf ,  Robert J. Wojnarowski ,  Charles W. Eichelberger

发明人： William P. Kornrumpf ,  Robert J. Wojnarowski ,  Charles W. Eichelberger

IPC分类号： H01L23/02 ,  H01L21/58 ,  H01L23/04 ,  H01L23/10 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H05K1/11

CPC分类号： H01L24/83 ,  H01L23/04 ,  H01L23/10 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L25/0655 ,  H01L2224/24137 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/3025

摘要： A body is hermetically sealed by electroplating a hermetic layer over the exterior surface of the body. A hermetic high density interconnect structure is provided by forming a continuous metal layer over the outermost dielectric layer of the multilayer interconnect structure and by disposing that continuous metal layer in a hermetically sealing relation to the substrate of the high density interconnect structure. A variety of techniques may be used for providing electrical feedthroughs between the interior and exterior of the hermetic enclosure as may a pseudo-hermetic enclosure in those situations where true hermeticity is not required.

摘要翻译： 通过在身体的外表面上电镀一层密封层，使身体密封。 通过在多层互连结构的最外层电介质层上形成连续的金属层，并通过将该连续金属层与高密度互连结构的衬底密封地设置，来提供密封的高密度互连结构。 可以使用各种技术来在密封外壳的内部和外部之间提供电馈通，如在不需要真实气密的那些情况下的伪密封封壳。

公开(公告)号：US5353498A

公开(公告)日：1994-10-11

申请号：US87434

申请日：1993-07-09

申请人： Raymond A. Fillion ,  Robert J. Wojnarowski ,  Michael Gdula ,  Herbert S. Cole ,  Eric J. Wildi ,  Wolfgang Daum

发明人： Raymond A. Fillion ,  Robert J. Wojnarowski ,  Michael Gdula ,  Herbert S. Cole ,  Eric J. Wildi ,  Wolfgang Daum

IPC分类号： H01L23/52 ,  H01L21/56 ,  H01L21/58 ,  H01L21/68 ,  H01L23/29 ,  H01L23/433 ,  H01L23/538 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H05K3/34

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/295 ,  H01L23/4334 ,  H01L23/538 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/2402 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/82039 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T29/49144

摘要： Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability. A portion of the chips and substrate molding material may be removed after the substrate molding material is hardened.

摘要翻译： 基板材料直接模制到半导体芯片和其他用于集成电路模块制造的电气部件。 具有接触垫的芯片面朝下放置在由基底支撑的粘合剂层上。 模具周围位于芯片周围。 在模具形式中加入基材成型材料，然后将基材成型材料硬化。 具有与预定接触焊盘对准的通孔并具有延伸通过通孔的电导体的通孔的电介质层位于硬化的基底成型材料和芯片的表面上。 在添加基板模制材料之前，可以将热塞固定到芯片的背面。 在添加基材模塑材料之前，连接器框架可以放置在粘合剂层上。 在添加基底成型材料之前，可以将电介质层放置在芯片的背面上以增强可修复性。 芯片和基材成型材料的一部分可以在基材模塑材料硬化之后被去除。

公开(公告)号：US5353195A

公开(公告)日：1994-10-04

申请号：US87433

申请日：1993-07-09

申请人： Raymond A. Fillion ,  Robert J. Wojnarowski

发明人： Raymond A. Fillion ,  Robert J. Wojnarowski

IPC分类号： H01L23/50 ,  H01L23/538 ,  H05K7/02

CPC分类号： H01L24/82 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

摘要： A multi-chip module includes a substrate supporting a plurality of chips. A dielectric layer which overlies the chips and the substrate has a connection surface and a substrate surface with metallization planes having plane openings patterned on each surface and vias aligned with predetermined pads on the chips and predetermined portions of the metallization plane of the substrate surface. An adhesive layer is situated between the substrate and the substrate surface of the dielectric layer, and a pattern of electrical conductors extends through the vias to interconnect selected chips and selected portions of the metallization planes. In a related design, the dielectric layer may be a board having chip openings and conductive through-connections aligned with predetermined portions of the metallization plane of the substrate surface. The board can be thick enough that chip wells are not necessary for each chip, in which case, a base dielectric layer having vias aligned with chip pads, through-connections and the connection surface overlies the board and supports a pattern of electrical conductors which interconnect the chips and metallization planes.

摘要翻译： 多芯片模块包括支撑多个芯片的基板。 覆盖芯片和衬底的电介质层具有连接表面和衬底表面，其中金属化平面具有在每个表面上图案化的平面开口，并且与衬底表面的芯片和金属化平面的预定部分上的预定焊盘对准的通孔。 粘合剂层位于基底和介电层的基底表面之间，并且电导体的图形延伸穿过通孔以互连选定的切屑和金属化平面的选定部分。 在相关设计中，电介质层可以是具有芯片开口和与衬底表面的金属化平面的预定部分对准的导电贯穿连接的板。 板可以足够厚，使得每个芯片不需要芯片阱，在这种情况下，具有与芯片焊盘，通孔连接对准的通孔的基底介电层，并且连接表面覆盖在板上并且支撑电连接的图案 芯片和金属化平面。

公开(公告)号：US5348607A

公开(公告)日：1994-09-20

申请号：US20913

申请日：1993-02-22

申请人： Robert J. Wojnarowski ,  Charles W. Eichelberger

发明人： Robert J. Wojnarowski ,  Charles W. Eichelberger

IPC分类号： H01L21/58 ,  H01L23/538 ,  B32B31/00

CPC分类号： H01L24/83 ,  H01L23/5389 ,  H01L24/29 ,  H01L2224/2919 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  Y10T156/109 ,  Y10T156/1092 ,  Y10T156/1111

摘要： A mixture for affixing dice to a substrate includes a thermoplastic polyimide, a solvent for the polyimide, and a solvent which does not dissolve the polyimide but adds thixotropicity to the mixture. The mixture is applied to the substrate, the dice are placed thereon, and the solvents are evaporated to bond the dice to the substrate. The bond is radiation hard and exhibits high shear pull strength. A poor solvent for the polyimide, sprayed over the dice and exposed portions of die attach material, causes some polyimide to precipitate out of solution in the exposed portions of die attach material to form a grid that extends between the dice and prevents the dice from "swimming together" during high temperature processing. In a solvent die-attachment method, the substrate is first coated with a mixture of die attach material, and the mixture is dried. Spraying a solvent over the die attach material causes the material to soften so that the dice applied thereto may adhere. The die attach material is then dried to form the bond.

摘要翻译： 用于将骰子固定到基底的混合物包括热塑性聚酰亚胺，聚酰亚胺的溶剂和不溶解聚酰亚胺但对混合物具有触变性的溶剂。 将混合物施加到基底上，将骰子放置在其上，并蒸发溶剂以将骰子结合到基底。 该粘合剂是辐射硬的并且表现出高的剪切拉力。 用于聚酰亚胺的不良溶剂喷涂在芯片附着材料的骰子和暴露部分上，导致一些聚酰亚胺从裸片附着材料的暴露部分中沉淀出溶液中以形成在骰子之间延伸的网格，并防止骰子“ 在高温加工过程中一起游泳。 在溶剂模具附着方法中，首先用基片附着材料的混合物涂覆基板，并将混合物干燥。 在模具附着材料上喷涂溶剂导致材料软化，使得施加到其上的骰子可以粘附。 然后将管芯附着材料干燥以形成粘合。