公开(公告)号：US09668344B2

公开(公告)日：2017-05-30

申请号：US14878891

申请日：2015-10-08

Applicant: SK hynix Inc.

Inventor： Won Duck Jung ,  Jong Ho Lee ,  Joo Hyun Kang ,  Chong Ho Cho ,  In Chul Hwang

IPC: H05K7/00 ,  H05K7/12 ,  H05K1/11 ,  H01L27/115 ,  H05K1/14 ,  H05K3/32

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L27/115 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81897 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/3511 ,  H05K1/145 ,  H05K3/32 ,  H05K3/325 ,  H05K2201/09209 ,  H05K2201/10159 ,  H05K2201/10287 ,  H05K2201/10613 ,  H05K2201/10757 ,  H05K2201/1078 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099

Abstract: A semiconductor package may include a first substrate including a first connection portion disposed on a surface of the first substrate and a second substrate including a second connection portion disposed on a surface of the second substrate. The second substrate may be disposed over the first substrate and the second connection portion facing the first connection portion. A first connection loop portion may be provided to include an end connected to the first connection portion. A second connection loop portion may be provided to include one end connected to the second connection portion and the other end combined with the first connection loop portion.

公开(公告)号：US09543384B2

公开(公告)日：2017-01-10

申请号：US14850385

申请日：2015-09-10

Applicant: SK hynix Inc.

Inventor： Han Jun Bae ,  Won Duck Jung

IPC: H01L23/495 ,  H01L25/065 ,  H01L29/06 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L29/0657 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/10158 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. Interconnection members are disposed to electrically connect the elastic buffer layer to the substrate. Each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.

Abstract translation: 半导体器件包括衬底，设置在衬底的表面上的弹性缓冲层，布置在弹性缓冲层的第一表面上的布线图案，以及布置在弹性缓冲层的背离弹性缓冲层的第二表面上的半导体芯片 弹性缓冲层的第一表面。 半导体芯片包括形成在面向弹性缓冲层的表面上的沟槽。 互连构件被设置为将弹性缓冲层电连接到衬底。 每个互连构件的一端电连接到一个布线图案，另一端电连接到基板。

公开(公告)号：US10741529B2

公开(公告)日：2020-08-11

申请号：US16237292

申请日：2018-12-31

Applicant: SK hynix Inc.

Inventor： Won Duck Jung ,  Sung Ho Hyun ,  Ju Il Eom

IPC: H01L25/07 ,  H01L23/535 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065

Abstract: A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.

公开(公告)号：US10157858B2

公开(公告)日：2018-12-18

申请号：US15856695

申请日：2017-12-28

Applicant: SK hynix Inc.

Inventor： Won Duck Jung ,  Sang Joon Lim ,  Sung Mook Lim

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/482

Abstract: Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.

公开(公告)号：US09345136B1

公开(公告)日：2016-05-17

申请号：US14716452

申请日：2015-05-19

Applicant: SK hynix Inc.

Inventor： Seung Jee Kim ,  Won Duck Jung

IPC: H05K1/02 ,  H05K1/11 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/48 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15313 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09472 ,  H05K2203/049 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A package substrate includes a core layer, first external interconnection lines on a top surface of the core layer, and internal interconnection lines. The first external interconnection lines include a first outermost external interconnection line on an edge of the core layer, and the internal interconnection lines include an outermost internal interconnection line in the edge of the core layer. A first bonding pad is disposed on the first outermost external interconnection line and exposed in a first bonding region of the core layer. A second bonding pad is disposed on the outermost internal interconnection line and exposed in a second bonding region of the core layer. The first bonding region is spaced apart from a chip attachment region by a first distance, and the second bonding region is spaced apart from the chip attachment region by a second distance greater than the first distance.

Abstract translation: 封装基板包括芯层，芯层顶表面上的第一外部互连线和内部互连线。 第一外部互连线包括在芯层的边缘上的第一最外部外部互连线，并且内部互连线包括在芯层的边缘中的最外部的内部互连线。 第一接合焊盘设置在第一最外部外部互连线上并暴露在芯层的第一接合区域中。 第二接合焊盘设置在最外部的内部互连线上并暴露在芯层的第二接合区域中。 第一接合区域与芯片连接区域间隔开第一距离，并且第二接合区域与芯片连接区域间隔开大于第一距离的第二距离。

公开(公告)号：US12131997B2

公开(公告)日：2024-10-29

申请号：US17844337

申请日：2022-06-20

Applicant: SK hynix Inc.

Inventor： Won Duck Jung

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/552 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/5286 ,  H01L23/528 ,  H01L23/552 ,  H01L24/05 ,  H01L24/46 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

公开(公告)号：US11233033B2

公开(公告)日：2022-01-25

申请号：US16899149

申请日：2020-06-11

Applicant: SK hynix Inc.

Inventor： Won Duck Jung

IPC: H01L25/065

Abstract: A semiconductor package includes a package substrate, a base module disposed on the package substrate and configured to include an intermediate chip, bonding wires connecting the intermediate chip to the package substrate, a lower-left chip disposed between the base module and the package substrate, and an upper-left chip disposed on the base module. The base module further includes an encapsulant encapsulating the intermediate chip, through vias electrically connected to the upper-left chip, and redistributed lines (RDLs) connecting the intermediate chip to the through vias and extending to provide connection parts which are spaced apart from the through vias and are connected to the lower-left chip.

公开(公告)号：US10224314B2

公开(公告)日：2019-03-05

申请号：US15280404

申请日：2016-09-29

Applicant: SK hynix Inc.

Inventor： Won Duck Jung ,  Sung Ho Hyun ,  Ju Il Eom

IPC: H01L25/07 ,  H01L23/535 ,  H01L23/498 ,  H01L23/31

Abstract: A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.