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18 条记录 (耗时 0.021 秒)

    Electronic package with offset reference plane cutout
    1.
    发明授权
    Electronic package with offset reference plane cutout 有权
    电子封装带偏置参考平面切口

    公开(公告)号：US06713853B1

    公开(公告)日：2004-03-30

    申请号：US10202322

    申请日：2002-07-23

    申请人： Siamak Fazelpour ,  Michel Fleury ,  Mark Patterson

    发明人： Siamak Fazelpour ,  Michel Fleury ,  Mark Patterson

    IPC分类号： H01L2302

    CPC分类号： H01L23/66 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K3/3436 ,  H01L2924/00

    摘要： An electronic package, such as a ball grid array (“BGA”) package, includes a high speed signal trace formed at a conductive layer and a corresponding reference plane formed at another conductive layer. The reference plane includes a cutout region formed therein; the cutout region is positioned over the signal solder ball to which the high speed signal trace is coupled. The lateral center point of the cutout region is offset relative to the lateral center point of the signal solder ball. The offset configuration reduces the capacitance between the signal solder ball and the reference plane and improves the high frequency transmission characteristics of the electronic package.

    摘要翻译： 诸如球栅阵列（“BGA”）封装的电子封装包括形成在导电层处的高速信号迹线和形成在另一导电层处的对应参考平面。 参考平面包括形成在其中的切口区域; 切口区域位于耦合有高速信号迹线的信号焊球上方。 切口区域的横向中心点相对于信号焊球的横向中心点偏移。 偏移配置降低了信号焊球和参考平面之间的电容，并改善了电子封装的高频传输特性。

    Fanned out interconnect via structure for electronic package substrates
    2.
    发明授权
    Fanned out interconnect via structure for electronic package substrates 有权
    用于电子封装衬底的扇形互连通孔结构

    公开(公告)号：US06812576B1

    公开(公告)日：2004-11-02

    申请号：US10145496

    申请日：2002-05-14

    申请人： Siamak Fazelpour ,  Mark Patterson

    发明人： Siamak Fazelpour ,  Mark Patterson

    IPC分类号： H01L2348

    CPC分类号： H05K1/115 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/1903 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0222 ,  H05K2201/096 ,  H01L2924/00

    摘要： An interconnect via structure according to the present invention can be used to support high frequency broadband signal transmission. The interconnect vias progressively increase in size and pitch from the signal source layer of the package substrate to the terminal pad layer of the package substrate. Each interconnect via includes a plurality of conductive sections formed at different substrate layers. At each substrate layer, the size and pitch of the vias result in a specified impedance. In a practical embodiment, the via impedance at each substrate layer is constant (e.g., 50 ohms). The interconnect structure can maintain a constant impedance while transitioning from a relatively narrow pitch at the signal source layer to a relatively wide pitch at the terminal layer, which may correspond to the pitch of the package substrate solder balls.

    摘要翻译： 根据本发明的互连通孔结构可用于支持高频宽带信号传输。 互连通孔从封装衬底的信号源层到封装衬底的端子焊盘层的尺寸和间距逐渐增加。 每个互连通孔包括形成在不同衬底层处的多个导电部分。 在每个衬底层处，通孔的尺寸和间距导致指定的阻抗。 在实际的实施例中，每个衬底层处的通路阻抗是恒定的（例如，50欧姆）。 互连结构可以保持恒定的阻抗，同时在信号源层处从相对较窄的间距转变到端子层处的相对宽的间距，这可能对应于封装衬底焊球的间距。

    Transformer comprising stacked inductors
    3.
    发明授权
    Transformer comprising stacked inductors 有权
    变压器包括堆叠电感器

    公开(公告)号：US06608363B1

    公开(公告)日：2003-08-19

    申请号：US09797307

    申请日：2001-03-01

    申请人： Siamak Fazelpour

    发明人： Siamak Fazelpour

    IPC分类号： H01L2900

    CPC分类号： H01F17/0006 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/292 ,  H01L27/08

    摘要： A transformer fabricated over a semiconductor die has been disclosed. A disclosed embodiment comprises a first inductor fabricated over a first bond pad. The first inductor is electrically connected to the first bond pad. For example, the bond pad can comprise copper, aluminum, copper-aluminum alloy, or gold. The disclosed embodiment further comprises a dielectric deposited over the first inductor. The disclosed embodiment further comprises a second inductor fabricated over the dielectric. For example, the dielectric can comprise BCB or low-k polyimide. Also, by way of example, the first and the second inductor can comprise copper, aluminum, copper-aluminum alloy, or gold.

    摘要翻译： 已经公开了在半导体管芯上制造的变压器。 所公开的实施例包括在第一接合焊盘上制造的第一电感器。 第一电感器电连接到第一接合焊盘。 例如，接合焊盘可以包括铜，铝，铜 - 铝合金或金。 所公开的实施例还包括沉积在第一电感器上的电介质。 所公开的实施例还包括在电介质上制造的第二电感器。 例如，电介质可以包括BCB或低k聚酰亚胺。 另外，作为示例，第一和第二电感器可以包括铜，铝，铜 - 铝合金或金。

    Voltage regulation for semiconductor dies and related structure
    5.
    发明授权
    Voltage regulation for semiconductor dies and related structure 有权
    半导体管芯电压调节及相关结构

    公开(公告)号：US06674646B1

    公开(公告)日：2004-01-06

    申请号：US09971162

    申请日：2001-10-05

    申请人： Khosrow Golshan ,  Siamak Fazelpour ,  Hassan S. Hashemi

    发明人： Khosrow Golshan ,  Siamak Fazelpour ,  Hassan S. Hashemi

    IPC分类号： H05K702

    CPC分类号： H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.

    摘要翻译： 电压调节器的输出是与包装衬底上的管芯附着区相邻的核心电压线。 电压调节器的输入通常耦合到电源，在一个实施例中，电源也是与芯片附接区域相邻的I / O电压线。 在一个实施例中，芯电压线被成形为环绕包装衬底上的管芯附着区域的环。 在另一个实施例中，I / O电压线也被成形为环绕包装衬底上的管芯附着区域的环。 此外，具有至少一个I / O Vdd接合焊盘和至少一个芯Vdd接合焊盘的半导体管芯可以安装在管芯附着区域中。 I / O Vdd接合焊盘和内核Vdd接合焊盘可以分别连接到I / O电压环和核心电压环。

    Package substrate interconnect layout for providing bandpass/lowpass filtering
    6.
    发明授权
    Package substrate interconnect layout for providing bandpass/lowpass filtering 有权
    封装衬底互连布局，用于提供带通/低通滤波

    公开(公告)号：US06617943B1

    公开(公告)日：2003-09-09

    申请号：US09919273

    申请日：2001-07-27

    申请人： Siamak Fazelpour

    发明人： Siamak Fazelpour

    IPC分类号： H01P120

    CPC分类号： H01P1/20

    摘要： An electronic device package includes a multilayer substrate having an interconnect structure configured to propagate a high frequency signal from one metal layer to another metal layer. The configuration and layout of the interconnect structure, particularly the arrangement of the reference vias associated with the signal via, is selected such that a desired filter response is achieved. The filter response is realized without any additional capacitor or inductor components. Thus, the natural discontinuity created by the vias and the inherent parasitic capacitance and inductance associated with the vias can be utilized to create a desired lowpass or bandpass filter response.

    摘要翻译： 电子器件封装包括具有互连结构的多层衬底，其被配置为将高频信号从一个金属层传播到另一个金属层。 选择互连结构的配置和布局，特别是与信号通孔相关联的参考通孔的布置，使得实现期望的滤波器响应。 无需额外的电容器或电感器元件实现滤波器响应。 因此，可以利用由过孔产生的自然不连续性和与过孔相关联的固有寄生电容和电感，以产生期望的低通或带通滤波器响应。

    Low inductance top metal layer design
    8.
    发明授权
    Low inductance top metal layer design 有权
    低电感顶层金属层设计

    公开(公告)号：US06274925B1

    公开(公告)日：2001-08-14

    申请号：US09358579

    申请日：1999-07-21

    申请人： Siamak Fazelpour

    发明人： Siamak Fazelpour

    IPC分类号： H01L2302

    CPC分类号： H01L24/49 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/645 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48463 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

    摘要： A substrate based package design for semiconductor chips is disclosed which reduces ground loop inductance. The design includes a substrate having a metal layer providing electrical interconnections. The metal layer includes a first conductive area adapted to provide an electrical ground, and a second conductive area adapted to provide an electrical connection to a power supply voltage. The first conductive area has a plurality of first conductive finger extensions providing electrical connections to vias for the electrical ground, and the second conductive area has a plurality of second conductive finger extensions providing electrical connections to vias for the power supply voltage. The first finger extensions and the second finger extensions are interlaced with each other. In accordance with another aspect of the invention, an internal conductive ring for ground is provided, with a concentric outer conductive ring for power supply connections. Further, each respective ring has conductive finger extensions in an interlaced comb configuration.

    摘要翻译： 公开了用于半导体芯片的基于衬底的封装设计，其降低了接地回路电感。 该设计包括具有提供电互连的金属层的基板。 金属层包括适于提供电接地的第一导电区域和适于提供与电源电压的电连接的第二导电区域。 第一导电区域具有多个第一导电指状延伸部，其提供与用于电接地的通路的电连接，并且第二导电区域具有多个第二导电指状延伸部，其提供与用于电源电压的通孔的电连接。 第一指状延伸部和第二指状延伸部彼此交织。根据本发明的另一方面，提供了一种用于接地的内部导电环，具有用于电源连接的同心外部导电环。 此外，每个环在隔行梳状配置中具有导电指状延伸部。