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14 条记录 (耗时 0.039 秒)

    Embedded multilayer chip capacitor and printed circuit board having the same
    5.
    发明授权
    Embedded multilayer chip capacitor and printed circuit board having the same 有权
    嵌入式多层片式电容器和具有相同功能的印刷电路板

    公开(公告)号：US07499258B2

    公开(公告)日：2009-03-03

    申请号：US11319722

    申请日：2005-12-29

    申请人： Chang Hoon Shim ,  Jin Yong An ,  Suk Hyeon Cho ,  Sung Hyung Kang

    发明人： Chang Hoon Shim ,  Jin Yong An ,  Suk Hyeon Cho ,  Sung Hyung Kang

    IPC分类号： H01G4/236 ,  H01G4/06

    CPC分类号： H01G2/06 ,  H01G4/232 ,  H01G4/30 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10643 ,  H01L2924/00

    摘要： The invention provides an embedded multilayer chip capacitor, and a printed circuit board having the same. The embedded multilayer chip capacitor has a capacitor body having a plurality of dielectric layers stacked one on another; a plurality of first and second internal electrodes formed inside the capacitor body, separated by the dielectric layers; and first and second vias extended vertically inside the capacitor body. The first via is connected to the first internal electrodes and the second via is connected to the second internal electrodes. The first via is led to a bottom of the capacitor body and the second via is led to a top of the capacitor body.

    摘要翻译： 本发明提供一种嵌入式多层片状电容器及具有该电容器的印刷电路板。 嵌入式多层片状电容器具有电容器主体，该电容器本体具有彼此层叠的多个电介质层; 多个第一和第二内部电极，形成在电容器本体内部，被电介质层分隔开; 并且第一和第二通孔在电容器体内垂直延伸。 第一通孔连接到第一内部电极，第二通孔连接到第二内部电极。 第一通孔被引导到电容器主体的底部，第二通孔被引导到电容器主体的顶部。

    Method of manufacturing substrate using a carrier
    8.
    发明申请
    Method of manufacturing substrate using a carrier 失效
    使用载体制造衬底的方法

    公开(公告)号：US20110318480A1

    公开(公告)日：2011-12-29

    申请号：US13137631

    申请日：2011-08-30

    申请人： Ki Hwan Kim ,  Jin Yong An ,  Myung Sam Kang

    发明人： Ki Hwan Kim ,  Jin Yong An ,  Myung Sam Kang

    IPC分类号： H05K3/00

    CPC分类号： H05K3/0097 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2203/0156 ,  H05K2203/1536

    摘要： A method of manufacturing a substrate using a carrier, that includes preparing a carrier having a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; patterning the metal layers to form base circuit layers; forming buildup layers on the base circuit layers; executing a routing process to separate the insulating layers from the releasing layer; and forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.

    摘要翻译： 使用载体制造衬底的方法，其包括制备具有释放层的载体，以及顺序地设置在释放层两侧的绝缘层和金属层; 图案化金属层以形成基极电路层; 在基极电路层上形成积层; 执行布线过程以将绝缘层与释放层分离; 以及在堆积层上形成阻焊层，并在阻焊层和绝缘层中形成开口以露出焊盘。

    Method of manufacturing substrate using a carrier
    9.
    发明授权
    Method of manufacturing substrate using a carrier 失效
    使用载体制造衬底的方法

    公开(公告)号：US08677618B2

    公开(公告)日：2014-03-25

    申请号：US13137631

    申请日：2011-08-30

    申请人： Ki Hwan Kim ,  Jin Yong An ,  Myung Sam Kang

    发明人： Ki Hwan Kim ,  Jin Yong An ,  Myung Sam Kang

    IPC分类号： H05K3/02 ,  H05K3/10

    CPC分类号： H05K3/0097 ,  H05K3/0052 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2203/0156 ,  H05K2203/1536

    摘要： A method of manufacturing a substrate using a carrier, that includes preparing a carrier having a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; patterning the metal layers to form base circuit layers; forming buildup layers on the base circuit layers; executing a routing process to separate the insulating layers from the releasing layer; and forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.

    摘要翻译： 使用载体制造衬底的方法，其包括制备具有释放层的载体，以及顺序地设置在释放层两侧的绝缘层和金属层; 图案化金属层以形成基极电路层; 在基极电路层上形成积层; 执行布线过程以将绝缘层与释放层分离; 以及在堆积层上形成阻焊层，并在阻焊层和绝缘层中形成开口以露出焊盘。