公开(公告)号：US08188828B2

公开(公告)日：2012-05-29

申请号：US12486477

申请日：2009-06-17

申请人： Takashi Noma ,  Jun Sasaki ,  Kosuke Yamada

发明人： Takashi Noma ,  Jun Sasaki ,  Kosuke Yamada

IPC分类号： H01F5/00 ,  H01F27/30 ,  H01F27/28

CPC分类号： H01F17/0013 ,  H01F38/10 ,  H01G4/40

摘要： A multilayer electronic component that can suppress the formation of projections and depressions on a surface, and an electronic component unit including the multilayer electronic component, are provided. In the multilayer electronic component, coil electrodes (8) having a shape of ring-shaped wiring with a part removed therefrom are electrically connected to each other to constitute a coil (L). Magnetic layers (4) are stacked together with the plurality of coil electrodes (8). The coil electrodes (8a, 8c, 8e) having a radius r1 and the coil electrodes (8b, 8d) having a radius r2 that is smaller than the radius r1 may be alternately arranged in a stacking direction.

摘要翻译： 提供了能够抑制表面上的凹凸形成的多层电子部件和包括该多层电子部件的电子部件单元。 在多层电子部件中，具有从其去除部分的环状布线形状的线圈电极（8）彼此电连接以构成线圈（L）。 磁性层（4）与多个线圈电极（8）堆叠在一起。 具有半径r1的线圈电极（8a，8c，8e）和半径r2小于半径r1的线圈电极（8b，8d）可以沿堆叠方向交替排列。

公开(公告)号：US20120269327A1

公开(公告)日：2012-10-25

申请号：US13443054

申请日：2012-04-10

申请人： Kohei Okamoto ,  Atsushi Komoto ,  Hirokatsu Miyata ,  Wataru Kubo ,  Takashi Noma

发明人： Kohei Okamoto ,  Atsushi Komoto ,  Hirokatsu Miyata ,  Wataru Kubo ,  Takashi Noma

IPC分类号： G21K1/00

CPC分类号： G21K1/067 ,  G21K1/062

摘要： An X-ray waveguide includes a cladding and a core. The core has a periodic structure formed in at least one period direction. The periodic structure includes periodically arranged members made of material having different refractive index real parts. The core is surrounded by the cladding in the plane perpendicular to a wave-guiding direction. The Bragg angle obtained from the periodicity of the periodic structure is smaller than the total reflection critical angle at which X-rays are incident on the interface between the cladding and the core. The at least one period direction is the direction of at least one fundamental vector expressing the periodicity of the periodic structure in a plane of the core perpendicular to the wave-guiding direction.

摘要翻译： X射线波导包括包层和芯。 芯具有在至少一个周期方向上形成的周期性结构。 周期性结构包括由具有不同折射率实部的材料制成的周期性布置的构件。 芯在垂直于波导方向的平面中被包层包围。 从周期结构的周期性获得的布拉格角小于X射线入射在包层和芯之间的界面上的全反射临界角。 至少一个周期方向是表示在垂直于波导方向的芯的平面中表示周期性结构的周期性的至少一个基本矢量的方向。

公开(公告)号：US07981807B2

公开(公告)日：2011-07-19

申请号：US12051502

申请日：2008-03-19

申请人： Akira Suzuki ,  Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao ,  Shinzo Ishibe ,  Shigeki Otsuka ,  Keiichi Yamaguchi

发明人： Akira Suzuki ,  Takashi Noma ,  Hiroyuki Shinogi ,  Yukihiro Takao ,  Shinzo Ishibe ,  Shigeki Otsuka ,  Keiichi Yamaguchi

IPC分类号： H01L21/302

CPC分类号： H01L21/78 ,  H01L23/3114 ,  H01L23/482 ,  H01L23/49827 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2224/05599 ,  H01L2224/05099

摘要： Cost is reduced and reliability is improved with a CSP type semiconductor device. A glass substrate which works as a supporting plate is bonded through an adhesive to a first surface of a semiconductor wafer on which first wirings are formed. Thickness of the semiconductor wafer is reduced by back-grinding the semiconductor wafer on a second surface of the semiconductor wafer which is opposite to the first surface of the semiconductor wafer. The semiconductor wafer is wet-etched to remove bumps and dips on the second surface of the semiconductor wafer caused during the back-grinding. Then the second surface of the semiconductor wafer is etched to form a tapered groove. The semiconductor wafer is wet-etched to reduce bumps and dips caused by the etching and round a corner of the groove. The wet-etching improves coverage of insulation film, wiring and protection film and enhances yield and reliability of the semiconductor device.

摘要翻译： CSP型半导体器件降低成本并提高可靠性。 作为支撑板的玻璃基板通过粘合剂粘合到其上形成有第一布线的半导体晶片的第一表面。 半导体晶片的厚度通过在与半导体晶片的第一表面相对的半导体晶片的第二表面上的背面研磨半导体晶片来减少。 湿式蚀刻半导体晶片以去除在后研磨期间引起的半导体晶片的第二表面上的凸起和凹陷。 然后蚀刻半导体晶片的第二表面以形成锥形槽。 湿式蚀刻半导体晶片以减少由蚀刻引起的凸起和凹陷，并且绕着凹槽的一角。 湿蚀刻提高了绝缘膜，布线和保护膜的覆盖率，并提高了半导体器件的产量和可靠性。

公开(公告)号：US07919875B2

公开(公告)日：2011-04-05

申请号：US11956160

申请日：2007-12-13

申请人： Takashi Noma ,  Katsuhiko Kitagawa ,  Hisao Otsuka ,  Akira Suzuki ,  Yoshinori Seki ,  Yukihiro Takao ,  Keiichi Yamaguchi ,  Motoaki Wakui ,  Masanori Iida

发明人： Takashi Noma ,  Katsuhiko Kitagawa ,  Hisao Otsuka ,  Akira Suzuki ,  Yoshinori Seki ,  Yukihiro Takao ,  Keiichi Yamaguchi ,  Motoaki Wakui ,  Masanori Iida

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099

摘要： A manufacturing method of a semiconductor device formed in a chip size package is improved to enhance a yield and reliability. A window to expose first wirings is formed only in a region of a semiconductor substrate where the first wirings exist. As a result, area of the semiconductor substrate bonded to a supporting body through an insulation film and a resin is increased to prevent cracks in the supporting body and separation of the semiconductor substrate from the supporting body. A slit is formed along a dicing line after forming the window, the slit is covered with a protection film and then the semiconductor substrate is diced into individual semiconductor dice. Thus, separation on a cut surface or at an edge of the semiconductor dice, which otherwise would be caused by contact of the blade in the dicing can be prevented.

摘要翻译： 改进了以芯片尺寸封装形成的半导体器件的制造方法，以提高产量和可靠性。 仅在存在第一布线的半导体基板的区域中形成露出第一布线的窗口。 结果，增加了通过绝缘膜和树脂粘合到支撑体的半导体衬底的面积，以防止支撑体中的裂纹和半导体衬底与支撑体的分离。 在形成窗口之后沿着切割线形成狭缝，用保护膜覆盖狭缝，然后将半导体基板切割成单独的半导体管芯。 因此，可以防止在切割时由刀片接触而导致的半导体管芯的切割面或边缘处的分离。

公开(公告)号：US20100038742A1

公开(公告)日：2010-02-18

申请号：US12440864

申请日：2007-08-22

申请人： Yuichi Morita ,  Takashi Noma

发明人： Yuichi Morita ,  Takashi Noma

IPC分类号： H01L29/06 ,  H01L21/60

CPC分类号： H01L21/4853 ,  H01L2224/11

摘要： This invention is directed to offer a technology that makes it possible to form desired bump electrodes easily when the bump electrodes are to be formed at locations lowered by a step. There is formed an isolation layer 12 to isolate each of bump electrode forming regions 11. The isolation layer 12 is a resist layer, for example, and is formed by exposure and development processes, for example. Each of the bump electrode forming regions 11 is surrounded by the isolation layer 12 and a protection layer 10 that covers a side surface of a semiconductor substrate 2. Then, a printing mask 16 that has openings 15 at locations corresponding to the bump electrode forming regions 11 is placed above the semiconductor substrate 2. Next, solder 17 in paste form is applied to the printing mask 16. Then the solder 17 is applied to a metal layer 9 by moving a squeeze 18 at a constant speed. Bump electrodes 19 are obtained by heating, melting and re-crystallizing the solder 17 after removing the printing mask 16.

摘要翻译： 本发明的目的在于提供一种技术，使得当在要降低阶梯的位置处形成凸起电极时，可以容易地形成所需的凸块电极。 形成隔离层12以隔离突起电极形成区域11.隔离层12例如是抗蚀剂层，并且例如通过曝光和显影处理形成。 每个凸起电极形成区域11被隔离层12和覆盖半导体衬底2的侧表面的保护层10围绕。然后，在与凸起电极形成区域对应的位置处具有开口15的印刷掩模16 11被放置在半导体衬底2的上方。接下来，将糊状的焊料17施加到印刷掩模16上。然后通过以恒定速度移动挤压18将焊料17施加到金属层9。 在除去印刷掩模16之后，通过加热，熔化和再结晶焊料17获得凸起电极19。

公开(公告)号：US20090162750A1

公开(公告)日：2009-06-25

申请号：US12394736

申请日：2009-02-27

申请人： Soichiro Kawakami ,  Norishige Kakegawa ,  Akio Kashiwazaki ,  Toshiaki Aiba ,  Rie Ueno ,  Mikio Shimada ,  Kaoru Ojima ,  Takashi Noma

发明人： Soichiro Kawakami ,  Norishige Kakegawa ,  Akio Kashiwazaki ,  Toshiaki Aiba ,  Rie Ueno ,  Mikio Shimada ,  Kaoru Ojima ,  Takashi Noma

IPC分类号： H01M4/58 ,  H01M4/88

CPC分类号： H01M4/134 ,  H01G11/24 ,  H01G11/46 ,  H01G11/50 ,  H01M4/366 ,  H01M4/386 ,  H01M4/387 ,  H01M4/48 ,  H01M4/58 ,  H01M4/62 ,  H01M10/0525 ,  Y02E60/13 ,  Y10T428/259 ,  Y10T428/2927

摘要： A method of producing a material capable of electrochemically storing and releasing a large amount of lithium ions is provided. The material is used as an electrode material for a negative electrode, and includes silicon or tin primary particles composed of crystal particles each having a specific diameter and an amorphous surface layer formed of at least a metal oxide, having a specific thickness. Gibbs free energy when the metal oxide is produced by oxidation of a metal is smaller than Gibbs free energy when silicon or tin is oxidized, and the metal oxide has higher thermodynamic stability than silicon oxide or tin oxide. The method of producing the electrode material includes reacting silicon or tin with a metal oxide, reacting a silicon oxide or a tin oxide with a metal, or reacting a silicon compound or a tin compound with a metal compound to react with each other.

摘要翻译： 提供了能够电化学储存和释放大量锂离子的材料的制造方法。 该材料用作负极的电极材料，并且包括由具有特定直径的晶体颗粒和由具有特定厚度的至少一种金属氧化物形成的无定形表面层构成的硅或锡一次粒子。 金属氧化物当金属氧化时产生的吉布斯自由能小于硅或锡被氧化时的吉布斯自由能，并且金属氧化物比氧化硅或氧化锡具有更高的热力学稳定性。 制造电极材料的方法包括使硅或锡与金属氧化物反应，使氧化硅或氧化锡与金属反应，或使硅化合物或锡化合物与金属化合物反应，使其彼此反应。

公开(公告)号：US07508072B2

公开(公告)日：2009-03-24

申请号：US11529553

申请日：2006-09-29

申请人： Yuichi Morita ,  Shinzo Ishibe ,  Takashi Noma ,  Hisao Otsuka ,  Yukihiro Takao ,  Hiroshi Kanamori

发明人： Yuichi Morita ,  Shinzo Ishibe ,  Takashi Noma ,  Hisao Otsuka ,  Yukihiro Takao ,  Hiroshi Kanamori

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/562 ,  H01L23/564 ,  H01L2221/6834 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16237 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/00014

摘要： The invention prevents a pad electrode for external connection of a semiconductor device from being damaged. An electronic circuit, a first pad electrode connected to the electronic circuit, and a second pad electrode connected to the first pad electrode are formed on a semiconductor substrate. A first protection film is formed, covering the first pad electrode and having an opening on the second pad electrode only. A wiring layer is further formed, being connected to the back surface of the first pad electrode through a via hole penetrating the semiconductor substrate and extending from the via hole onto the back surface of the semiconductor substrate.

摘要翻译： 本发明防止半导体器件的外部连接的焊盘电极被损坏。 连接到电子电路的电子电路，第一焊盘电极和连接到第一焊盘电极的第二焊盘电极形成在半导体衬底上。 形成第一保护膜，覆盖第一焊盘电极并且仅在第二焊盘电极上具有开口。 进一步形成布线层，其通过穿透半导体衬底的通孔连接到第一焊盘电极的背面并从通孔延伸到半导体衬底的背面。

公开(公告)号：US20090039851A1

公开(公告)日：2009-02-12

申请号：US12064622

申请日：2007-04-04

申请人： Iwao Fukushi ,  Masahiro Maruki ,  Takashi Noma

发明人： Iwao Fukushi ,  Masahiro Maruki ,  Takashi Noma

IPC分类号： G05F1/618

CPC分类号： H02M3/1588 ,  H02M1/088 ,  H02M2001/0025 ,  Y02B70/1466 ,  Y10S323/901

摘要： A switching control circuit comprises: an error amplifying circuit configured to output an error voltage obtained by amplifying an error between a feedback voltage corresponding to an output voltage and a lower voltage selected out of a first reference voltage increasing with time passage and a second reference voltage used as a reference for a target level; a comparison circuit configured to output a comparison signal obtained by comparing the feedback voltage with the error voltage output from the error amplifying circuit; and a drive circuit configured to output first and second control signals for controlling first and second transistors, respectively, in order to turn the output voltage to the target level by complementarily turning on and off the first and second transistors, after the error voltage exceeds the feedback voltage, based on the comparison signal output from the comparison circuit.

摘要翻译： 一种开关控制电路，包括：误差放大电路，被配置为输出通过放大对应于输出电压的反馈电压与从时间通过而增加的第一参考电压中选择的较低电压之间的误差而获得的误差电压，以及第二参考电压 用作目标水平的参考; 比较电路，被配置为输出通过将反馈电压与从误差放大电路输出的误差电压进行比较而获得的比较信号; 以及驱动电路，被配置为输出用于分别控制第一和第二晶体管的第一和第二控制信号，以便在误差电压超过第一和第二晶体管之后通过互补地导通和关断第一和第二晶体管将输出电压转换到目标电平 反馈电压，基于比较电路输出的比较信号。

公开(公告)号：US20080277793A1

公开(公告)日：2008-11-13

申请号：US12111383

申请日：2008-04-29

申请人： Takashi Noma ,  Hiroyuki Shinogi ,  Noboru Okubo

发明人： Takashi Noma ,  Hiroyuki Shinogi ,  Noboru Okubo

IPC分类号： H01L23/485 ,  H01L21/768 ,  H01L21/58

CPC分类号： H01L23/3114 ,  H01L21/6835 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

摘要： A semiconductor device with improved moisture resistance and its manufacturing method as well as a manufacturing method of a semiconductor device which simplifies a manufacturing process and improves productivity are offered. This invention offers a CSP type semiconductor device and its manufacturing method that can prevent moisture and the like from infiltrating into it to attain high reliability by covering a side surface of a semiconductor chip with a thick protection layer. This invention also offers a highly productive manufacturing method of semiconductor devices by which a supporter bonded to semiconductor dice is etched from a back surface-side of the supporter so that the semiconductor devices can be separated without dicing.

摘要翻译： 提供了一种具有改善的耐湿性的半导体器件及其制造方法以及简化制造工艺并提高生产率的半导体器件的制造方法。 本发明提供一种CSP型半导体器件及其制造方法，其可以通过用厚保护层覆盖半导体芯片的侧表面来防止水分等渗入其中以获得高可靠性。 本发明还提供了一种高效率的半导体器件的制造方法，通过该半导体器件，从支撑体的背面侧蚀刻与半导体晶片接合的支撑体，使得可以在不切割的情况下分离半导体器件。

公开(公告)号：US20080258258A1

公开(公告)日：2008-10-23

申请号：US12103857

申请日：2008-04-16

申请人： Katsu HORIKOSHI ,  Hisayoshi Uchiyama ,  Takashi Noma ,  Yoshinori Seki ,  Hiroshi Yamada ,  Shinzo Ishibe ,  Hiroyuki Shinogi

发明人： Katsu HORIKOSHI ,  Hisayoshi Uchiyama ,  Takashi Noma ,  Yoshinori Seki ,  Hiroshi Yamada ,  Shinzo Ishibe ,  Hiroyuki Shinogi

IPC分类号： H01L29/92

CPC分类号： H01L23/642 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/5223 ,  H01L24/11 ,  H01L24/12 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/18 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/13099 ,  H01L2924/00

摘要： The invention provides a semiconductor device which has a capacitor element therein to achieve size reduction of the device, the capacitor element having larger capacitance than conventional. A semiconductor integrated circuit and pad electrodes are formed on the front surface of a semiconductor substrate. A second insulation film is formed on the side and back surfaces of the semiconductor substrate, and a capacitor electrode is formed between the back surface of the semiconductor substrate and the second insulation film, contacting the back surface of the semiconductor substrate. The second insulation film is covered by wiring layers electrically connected to the pad electrodes, and the wiring layers and the capacitor electrode overlap with the second insulation film being interposed therebetween. Thus, the capacitor electrode, the second insulation film and the wiring layers form capacitors.

摘要翻译： 本发明提供了一种半导体器件，其中具有电容器元件以实现器件的尺寸减小，电容器元件具有比常规更大的电容。 半导体集成电路和焊盘电极形成在半导体衬底的前表面上。 在半导体衬底的侧表面和后表面上形成第二绝缘膜，并且在半导体衬底的背面与第二绝缘膜之间形成电容电极，与半导体衬底的后表面接触。 第二绝缘膜由与焊盘电极电连接的布线层覆盖，并且布线层和电容器电极与第二绝缘膜重叠。 因此，电容器电极，第二绝缘膜和布线层形成电容器。