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    Electrical coupling of a stiffener to a chip carrier
    1.
    发明授权
    Electrical coupling of a stiffener to a chip carrier 有权
    加强筋与芯片载体的电耦合

    公开(公告)号：US06699736B2

    公开(公告)日：2004-03-02

    申请号：US10305643

    申请日：2002-11-26

    申请人： Terry J. Dornbos ,  Raymond A. Phillips, Jr. ,  Mark V. Pierson ,  William J. Rudik ,  David L. Thomas

    发明人： Terry J. Dornbos ,  Raymond A. Phillips, Jr. ,  Mark V. Pierson ,  William J. Rudik ,  David L. Thomas

    IPC分类号： H01L2144

    CPC分类号： H05K3/0061 ,  H01L21/4846 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09554 ,  H05K2201/10977

    摘要： A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate. The electrically conductive contact may include an electrically conductive adhesive or a metallic solder. Additional embodiments of the present invention form the adhesive layer by applying an electrically conductive adhesive on the substrate, wherein after the stiffener is placed on the adhesive layer, the electrically conductive adhesive mechanically and electrically couples the stiffener to the surface of the substrate.

    摘要翻译： 用于将金属加强件导电耦合到芯片载体的方法和结构。 衬底在其表面上具有导电焊盘，并且在衬底表面上形成粘合剂层。 金属加强件被放置在粘合剂层上，其中粘合剂层将加强件机械地连接到基底表面，并将加强件电耦合到垫。 然后将粘合剂层固化，例如通过在升高的温度下加压。 本发明的实施例通过在焊盘上形成导电触点并在基板上设置干燥的粘合剂来形成粘合剂层，使得导电触点位于干粘合剂中的孔内。 导电触头将加强件电耦合到焊盘。 固化步骤包括固化干燥粘合剂和导电接触，导致干燥粘合剂将加强剂粘合到基底上。 导电接触可包括导电粘合剂或金属焊料。 本发明的另外的实施方案通过在基底上施加导电粘合剂形成粘合剂层，其中在将加强件放置在粘合剂层上之后，导电粘合剂将加强件机械地和电耦合到基底的表面。

    Electrical coupling of a stiffener to a chip carrier
    2.
    发明授权
    Electrical coupling of a stiffener to a chip carrier 有权

    公开(公告)号：US06534848B1

    公开(公告)日：2003-03-18

    申请号：US09657194

    申请日：2000-09-07

    申请人： Terry J. Dornbos ,  Raymond A. Phillips, Jr. ,  Mark V. Pierson ,  William J. Rudik ,  David L. Thomas

    发明人： Terry J. Dornbos ,  Raymond A. Phillips, Jr. ,  Mark V. Pierson ,  William J. Rudik ,  David L. Thomas

    IPC分类号： H01L2302

    CPC分类号： H05K3/0061 ,  H01L21/4846 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09554 ,  H05K2201/10977

    摘要： A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate. The electrically conductive contact may include an electrically conductive adhesive or a metallic solder. Additional embodiments of the present invention form the adhesive layer by applying an electrically conductive adhesive on the substrate, wherein after the stiffener is placed on the adhesive layer, the electrically conductive adhesive mechanically and electrically couples the stiffener to the surface of the substrate.

    Method of fabricating a laminate circuit structure
    7.
    发明授权
    Method of fabricating a laminate circuit structure 失效
    制造层叠电路结构的方法

    公开(公告)号：US06834426B1

    公开(公告)日：2004-12-28

    申请号：US09625135

    申请日：2000-07-25

    申请人： Robert M. Japp ,  Gregory A. Kevern ,  William J. Rudik

    发明人： Robert M. Japp ,  Gregory A. Kevern ,  William J. Rudik

    IPC分类号： H05K320

    CPC分类号： H05K3/4641 ,  H05K3/4069 ,  H05K3/445 ,  H05K3/4614 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2201/10378 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165

    摘要： A method for fabricating a laminate circuit structure is provided. The method comprises: providing at least two modularized circuitized voltage plane subassemblies wherein each of the subassemblies comprise at least two signal planes having an external and internal surface disposed about an internal voltage plane; providing a dielectric material between the signal and voltage planes; and providing dielectric on each external surface of each signal plane; and providing a non-cured or partially cured curable dielectric composition between the subassemblies wherein the dielectric composition comprises, dielectric material that is of the same material as the dielectric material used in said subassemblies, aligning the subassemblies, and then laminating to cause bonding of the subassemblies.

    摘要翻译： 提供一种制造叠层电路结构的方法。 该方法包括：提供至少两个模块化的电路化电压平面子组件，其中每个子组件包括至少两个具有围绕内部电压平面设置的外部和内部表面的信号平面; 在信号和电压平面之间提供介电材料; 并在每个信号平面的每个外表面上提供电介质; 并且在所述子组件之间提供未固化或部分固化的可固化电介质组合物，其中所述电介质组合物包括与所述子组件中使用的介电材料具有相同材料的介电材料，对准所述子组件，然后层压以引起 子组件

    Circuit package having low modulus, conformal mounting pads
    8.
    发明授权
    Circuit package having low modulus, conformal mounting pads 失效
    具有低模数，适形安装垫的电路封装

    公开(公告)号：US06399896B1

    公开(公告)日：2002-06-04

    申请号：US09525379

    申请日：2000-03-15

    申请人： Frank J. Downes, Jr. ,  Donald S. Farquhar ,  Robert M. Japp ,  William J. Rudik

    发明人： Frank J. Downes, Jr. ,  Donald S. Farquhar ,  Robert M. Japp ,  William J. Rudik

    IPC分类号： H05K116

    CPC分类号： H05K3/326 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/114 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/10734 ,  H05K2203/0307

    摘要： Reliability of circuit packaging while accommodating larger chips and increased temperature excursions is achieved by use of compliant pads only at the locations of connections between packaging levels, preferably between a laminated chip carrier and a printed circuit board. The invention allows the coefficient of thermal expansion of the chip carrier to be economically well-matched to the CTE of the chip and accommodation of significant differences in CTEs of package materials to be accommodated at a single packaging level. The compliant pads are preferably of low aspect ratio which are not significantly deflected by accelerations and can be formed on a surface or recessed into it. Connections can be made through surface connections and/or plated through holes. Connection enhancements such as solder wettable surfaces or dendritic textures are provided in a conductive metal or alloy layer over a compliant rubber or elastomer layer which may be conductive or non-conductive.

    摘要翻译： 通过仅在封装层之间的连接位置（优选在层压芯片载体和印刷电路板之间）使用柔性焊盘来实现电路封装的可靠性，同时容纳更大的芯片和增加的温度漂移。 本发明允许芯片载体的热膨胀系数与芯片的CTE经济地良好匹配，并且可以容纳在单个封装层面上容纳的封装材料的CTE的显着差异。 柔性衬垫优选地具有低纵横比，其不被加速度显着偏转，并且可以形成在表面上或凹入其中。 可以通过表面连接和/或电镀通孔进行连接。 在导电金属或合金层中的柔性橡胶或弹性体层上提供诸如焊料可润湿表面或树枝状织构的连接增强，其可以是导电的或不导电的。