公开(公告)号：US5017973A

公开(公告)日：1991-05-21

申请号：US287738

申请日：1988-12-21

申请人： Hiroshi Mizuta ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

发明人： Hiroshi Mizuta ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

IPC分类号： H01L29/15 ,  H01L29/201 ,  H01L29/205 ,  H01L29/68 ,  H01L29/88

CPC分类号： B82Y10/00 ,  H01L29/155 ,  H01L29/882

摘要： A resonant tunneling device includes a superlattice layer which includes an interlaminated structure of three semiconductor layers each having a narrow energy bandgap and serving as a quantum well layer and four semiconductor layers each having a wide energy bandgap and serving as a barrier layer and in which three quantum levels are formed in the quantum well layers. A resonant tunneling phenomenon produced between the quantum levels provides peak current values which are substantially equal to each other, peak voltages which can be set independently from each other, and peak-to-valley (P/V) ratios which are high, thereby realizing a resonant tunneling device which has an excellent performance as a three state logic element for a logic circuit. By increasing the number of quantum well layers and the number of barrier layers, a logic element of four or more states can be realized for a logic circuit.

公开(公告)号：US5023687A

公开(公告)日：1991-06-11

申请号：US304210

申请日：1989-01-31

申请人： Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

发明人： Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8226 ,  H01L21/8228 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/082 ,  H01L27/12 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L21/8226 ,  H01L21/8252 ,  H01L27/0605

摘要： A complementary semiconductor device is disclosed having a substrate and a four layer structure of pnpn provided on the substrate wherein the first three layers constitute a pnp-type bipolar transistor and the second to the fourth layer constitute an npn-type bipolar transistor. According to the present invention, the pnp- and npn-type transistor which are disposed on different portions of a principal surface of the substrate, respectively, can be produced concurrently by crystal growth and thus production steps are simple and yield is remarkably improved.

公开(公告)号：US4983532A

公开(公告)日：1991-01-08

申请号：US286710

申请日：1988-12-20

申请人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi ,  Masayoshi Saito ,  Hiroshi Miyazaki ,  Fumio Murai

发明人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi ,  Masayoshi Saito ,  Hiroshi Miyazaki ,  Fumio Murai

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

CPC分类号： H01L29/66318 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072 ,  Y10S148/10

摘要： Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

摘要翻译： 可以通过使用通过包括通过在化合物上的外延生长分别连续生长用作子集电极，集电极，基极和发射极的半导体层的工艺形成的平面异质结双极晶体管来实现器件的微结构和大规模集成 半导体衬底，其中发射极结和集电极结中的至少一个是异质结，其中通过选择性CVD法形成集电体引出金属层。

公开(公告)号：US5017517A

公开(公告)日：1991-05-21

申请号：US518035

申请日：1990-05-02

申请人： Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chushirou Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani

发明人： Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chushirou Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/28 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L29/80

CPC分类号： H01L29/66318 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02491 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/28 ,  Y10S148/005 ,  Y10S148/011 ,  Y10S148/026 ,  Y10S438/976

摘要： A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一半导体层，形成锑（Sb）的表面保护层或具有Sb的材料作为其主要成分，执行制造所需的其它步骤 半导体器件，去除表面保护层，并且在由此暴露的第一半导体层上形成第二半导体层。

公开(公告)号：US5258631A

公开(公告)日：1993-11-02

申请号：US884878

申请日：1992-05-18

申请人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

发明人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L27/06 ,  H01L29/737 ,  H01L29/778 ,  H01L29/06 ,  H01L29/167 ,  H01L29/30 ,  H01L31/072

CPC分类号： H01L29/66318 ,  H01L21/182 ,  H01L21/28587 ,  H01L27/0605 ,  H01L29/66462 ,  H01L29/7373 ,  H01L29/7787

摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.

摘要翻译： 本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。 前者通过应用其源极和漏极区域的形成来制造通过引入杂质例如通过离子注入引起异质结的紊乱的技术或通过形成由 选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。 后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。 这些半导体器件可以降低源极栅极电阻和寄生基极电阻。 本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

公开(公告)号：US5229623A

公开(公告)日：1993-07-20

申请号：US746288

申请日：1991-08-13

申请人： Tomonori Tanoue ,  Hiroshi Mizuta ,  Susumu Takahashi

发明人： Tomonori Tanoue ,  Hiroshi Mizuta ,  Susumu Takahashi

IPC分类号： G02F3/02 ,  G06N3/063 ,  G06N3/067 ,  G11C11/56

CPC分类号： B82Y10/00 ,  G02F3/028 ,  G06N3/0635 ,  G06N3/0675 ,  G11C11/56 ,  G11C13/04 ,  G11C2211/5614

摘要： A semiconductor device is disclosed, which includes a multiple negative differential resistance element having negative differential resistance characteristics at at least two places in the current-voltage characteristics, and which is suitable for constructing a neural network having a high density integration and a high reliability.

摘要翻译： 公开了一种半导体器件，其包括在电流 - 电压特性中的至少两个位置具有负的差分电阻特性的多个负的差分电阻元件，并且适用于构建具有高密度集成和高可靠性的神经网络。

公开(公告)号：US5381027A

公开(公告)日：1995-01-10

申请号：US134622

申请日：1993-10-12

申请人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

发明人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L27/06 ,  H01L29/737 ,  H01L29/778 ,  H01L29/804 ,  H01L29/784

CPC分类号： H01L29/66318 ,  H01L21/182 ,  H01L21/28587 ,  H01L27/0605 ,  H01L29/66462 ,  H01L29/7373 ,  H01L29/7787

摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.

摘要翻译： 本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。 前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由 选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。 后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。 这些半导体器件可以降低源极栅极电阻和寄生基极电阻。 本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

公开(公告)号：US5019524A

公开(公告)日：1991-05-28

申请号：US401506

申请日：1989-08-30

申请人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushiro Kusano ,  Masayoshi Kobayashi ,  Susumu Takahashi

发明人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushiro Kusano ,  Masayoshi Kobayashi ,  Susumu Takahashi

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/1004 ,  H01L29/7371 ,  Y10S148/01 ,  Y10S148/072 ,  Y10S148/084

摘要： Disclosed is a semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer and the surface of an emitter-base junction are covered with a high-resistivity layer of compound semiconductor containing at least one constituent element common to an emitter layer and the base layer.

公开(公告)号：US20120208476A1

公开(公告)日：2012-08-16

申请号：US13451850

申请日：2012-04-20

申请人： Tomonori Tanoue ,  Hidetoshi Matsumoto

发明人： Tomonori Tanoue ,  Hidetoshi Matsumoto

IPC分类号： H04B1/04 ,  H04B1/034

CPC分类号： H03G3/3042 ,  H03F1/0261 ,  H03F3/191 ,  H03F3/24 ,  H03F2200/105 ,  H03F2200/207 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/471 ,  H03F2200/99

摘要： A high frequency power amplifier maintains an excellent linearity regardless of a fluctuation of a load impedance and is downsized. The high frequency power amplifier detects an AC voltage amplitude at an output terminal of a final amplification stage transistor, and suppresses an input signal amplitude of a power amplifier when the voltage amplitude exceeds a predetermined threshold value.

摘要翻译： 无论负载阻抗的波动如何，高频功率放大器保持良好的线性度，并且小型化。 高频功率放大器检测最终放大级晶体管的输出端的交流电压振幅，并且当电压振幅超过预定阈值时，抑制功率放大器的输入信号振幅。

公开(公告)号：US20070190962A1

公开(公告)日：2007-08-16

申请号：US11618207

申请日：2006-12-29

申请人： Kenji Sasaki ,  Tomonori Tanoue ,  Sakae Kikuchi ,  Toshifumi Makino ,  Takeshi Sato ,  Tsutomu Kobori ,  Yasunari Umemoto ,  Takashi Kitahara

发明人： Kenji Sasaki ,  Tomonori Tanoue ,  Sakae Kikuchi ,  Toshifumi Makino ,  Takeshi Sato ,  Tsutomu Kobori ,  Yasunari Umemoto ,  Takashi Kitahara

IPC分类号： H04B1/06 ,  H04B1/28 ,  H04B7/00

CPC分类号： H04B1/28 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L24/85 ,  H01L25/18 ,  H01L2223/6644 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).

摘要翻译： 提供了一种技术，使得用于蜂窝电话等的RF模块的尺寸可以减小。 在构成RF模块的布线板上，设置有形成放大器电路的第一半导体芯片和形成用于控制放大器电路的控制电路的第二半导体芯片。 第二半导体芯片上的接合焊盘通过导线直接通过第一半导体芯片上的接合焊盘连接而不使用继电器垫。 在这方面，形成在第一半导体芯片上的焊盘不是正方形，而是矩形（长方形）。