Wafer Level Chip Scale Package with Reduced Stress on Solder Balls
    3.
    发明申请
    Wafer Level Chip Scale Package with Reduced Stress on Solder Balls 有权
    晶圆级芯片级封装,减少了焊球的应力

    公开(公告)号:US20120319270A1

    公开(公告)日:2012-12-20

    申请号:US13162394

    申请日:2011-06-16

    IPC分类号: H01L23/48

    摘要: A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

    摘要翻译: 一种结构包括半导体衬底上的金属焊盘,具有金属焊盘上方的一部分的钝化层以及钝化层上的第一聚酰亚胺层,其中第一聚酰亚胺层具有第一厚度和第一杨氏模量。 后钝化互连(PPI)包括在第一聚酰亚胺层之上的第一部分,以及延伸到钝化层和第一聚酰亚胺层中的第二部分。 PPI电耦合到金属垫。 第二个聚酰亚胺层位于PPI之上。 第二聚酰亚胺层具有第二厚度和第二杨氏模量。 厚度比和杨氏模量比中的至少一个大于1.0,其中厚度比是第一厚度与第二厚度的比率,杨氏模量比是第二杨氏模量与第一杨氏模量之比 模数。

    Die carrier for package on package assembly
    5.
    发明授权
    Die carrier for package on package assembly 有权
    封装组件上的封装的载体

    公开(公告)号:US08927333B2

    公开(公告)日:2015-01-06

    申请号:US13302059

    申请日:2011-11-22

    摘要: A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

    摘要翻译: 提供了一种用于在回流操作期间维持管芯对准的封装封装布置。 第一顶模具有焊料凸块的第一布置。 底部封装具有电连接到第一焊料凸点布置的第一电气布置。 模具载体具有限定在其底表面上的多个安装区域,其中第一顶模在多个安装区域中的第一个处粘附到模具载体。 具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。 焊料凸块的第一和第二布置彼此对称,其中在回流操作期间平衡表面张力,并且通常相对于底部封装固定模具载体的取向。

    Wafer level chip scale package with reduced stress on solder balls
    6.
    发明授权
    Wafer level chip scale package with reduced stress on solder balls 有权
    晶圆级芯片级封装,焊球应力减小

    公开(公告)号:US08373282B2

    公开(公告)日:2013-02-12

    申请号:US13162394

    申请日:2011-06-16

    IPC分类号: H01L23/52 H01L23/48 H01L29/40

    摘要: A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus.

    摘要翻译: 一种结构包括半导体衬底上的金属焊盘,具有金属焊盘上方的一部分的钝化层以及钝化层上的第一聚酰亚胺层,其中第一聚酰亚胺层具有第一厚度和第一杨氏模量。 后钝化互连(PPI)包括在第一聚酰亚胺层之上的第一部分,以及延伸到钝化层和第一聚酰亚胺层中的第二部分。 PPI电耦合到金属垫。 第二个聚酰亚胺层位于PPI之上。 第二聚酰亚胺层具有第二厚度和第二杨氏模量。 厚度比和杨氏模量比中的至少一个大于1.0,其中厚度比是第一厚度与第二厚度的比率,杨氏模量比是第二杨氏模量与第一杨氏模量之比 模数。

    DIE CARRIER FOR PACKAGE ON PACKAGE ASSEMBLY
    7.
    发明申请
    DIE CARRIER FOR PACKAGE ON PACKAGE ASSEMBLY 有权
    用于包装组件的包装盒

    公开(公告)号:US20130127040A1

    公开(公告)日:2013-05-23

    申请号:US13302059

    申请日:2011-11-22

    摘要: A package-on-package arrangement for maintaining die alignment during a reflow operation is provided. A first top die has a first arrangement of solder bumps. A bottom package has a first electrical arrangement to electrically connect to the first arrangement of solder bumps. A die carrier has a plurality of mounting regions defined on its bottom surface, wherein the first top die is adhered to the die carrier at a first of the plurality of mounting regions. One of a second top die and a dummy die having a second arrangement of solder bumps is also fixed to the die carrier at a second of the plurality of mounting regions of the die carrier. The first and second arrangements of solder bumps are symmetric to one another, therein balancing a surface tension during a reflow operation, and generally fixing an orientation of the die carrier with respect to the bottom package.

    摘要翻译: 提供了一种用于在回流操作期间维持管芯对准的封装封装布置。 第一顶模具有焊料凸块的第一布置。 底部封装具有电连接到第一焊料凸点布置的第一电气布置。 模具载体具有限定在其底表面上的多个安装区域,其中第一顶模在多个安装区域中的第一个处粘附到模具载体。 具有第二排列焊料凸点的第二顶模和虚模具之一也在模具载体的多个安装区域的第二位置处固定到模具载体。 焊料凸块的第一和第二布置彼此对称,其中在回流操作期间平衡表面张力,并且通常相对于底部封装固定模具载体的取向。