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20 条记录 (耗时 0.018 秒)

    Method of silicon oxide and silicon glass films deposition
    1.
    发明授权
    Method of silicon oxide and silicon glass films deposition 有权
    氧化硅和硅玻璃膜沉积方法

    公开(公告)号：US06583069B1

    公开(公告)日：2003-06-24

    申请号：US09458729

    申请日：1999-12-13

    申请人： Vladislav Y. Vassiliev ,  John Leonard Sudijono

    发明人： Vladislav Y. Vassiliev ,  John Leonard Sudijono

    IPC分类号： H01L21316

    CPC分类号： B41J2/17553

    摘要： A method for fabricating a silicon oxide and silicon glass layers at low temperature using High Density Plasma CVD with silane or organic or inorganic silane derivatives as a source of silicon, inorganic compounds containing boron, phosphorus, and fluorine as doping compounds, oxygen, and gas additives is described. RF plasma with certain plasma density is maintained throughout the entire deposition step in a reactor chamber. A key feature of the invention's process is a mole ratio of gas additive to source of silicon, which is maintained in the range of about 0.3-20 depending on the compound used and the deposition process conditions. As a gas additive, one of the group including halide-containing organic compounds having the general formula CxHyRz, and chemical compounds with the double carbon-carbon bonds having the general formula CnH2n, is used. This feature provides the reaction conditions for the proper reaction performance that allows a deposition of a film with good film integrity and void-free gap-fill between the steps of device structures.

    摘要翻译： 使用硅烷或有机或无机硅烷衍生物作为硅源的高密度等离子体CVD制备氧化硅和硅玻璃层的方法，其中含有硼，磷和氟的无机化合物作为掺杂化合物，氧和气体 描述了添加剂。 在反应器室中的整个沉积步骤中保持具有一定等离子体密度的RF等离子体。 本发明方法的关键特征是气体添加剂与硅源的摩尔比，其保持在约0.3-20的范围内，这取决于所用的化合物和沉积工艺条件。 作为气体添加剂，使用具有通式C x H y R z的含卤化物的有机化合物和具有通式C n H 2n的双碳 - 碳键的化合物之一。 该特征提供了用于适当反应性能的反应条件，其允许在器件结构的步骤之间沉积具有良好膜完整性和无空隙间隙填充的膜。

    Method of fabrication of low leakage capacitor
    2.
    发明授权
    Method of fabrication of low leakage capacitor 失效
    低漏电容器的制造方法

    公开(公告)号：US6143598A

    公开(公告)日：2000-11-07

    申请号：US246893

    申请日：1999-02-08

    申请人： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

    发明人： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

    IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

    CPC分类号： H01L28/40 ,  H01L28/60 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852

    摘要： A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitrogen and oxygen are present, depositing a dielectric layer and submitting the top of the dielectric layer to plasma treatment in an oxidizing medium where nitrogen and oxygen are present. Various materials are used for the plasma treatment in an oxidizing medium where nitrogen and oxygen are present. While the present invention uses amorphous silicon as the dielectric material, plasma treatment in an oxidizing medium where nitrogen and oxygen are present can readily applied to a number of other dielectric materials. The objective in constructing capacitors for semiconductor circuits is to reduce the thickness of the dielectric material as much as possible and use a dielectric material for the dielectric which has a high dielectric constant, this increases the value of the capacitor electrical charge which can be carried by the capacitor. The objective of the present invention is to eliminate the leakage current between the plates of a capacitor so that the capacitor can maintain a high voltage between the top and the bottom plate.

    摘要翻译： 用于高密度半导体电路的半导体器件的电容器元件是通过形成电容器的底板的步骤形成的，将底板的顶部在存在氮和氧的氧化介质中进行等离子体处理， 介电层，并将介电层的顶部在存在氮和氧的氧化介质中进行等离子体处理。 在存在氮和氧的氧化介质中使用各种材料进行等离子体处理。 虽然本发明使用非晶硅作为介电材料，但在存在氮和氧的氧化介质中的等离子体处理可以容易地应用于许多其它电介质材料。 用于半导体电路构造电容器的目的是尽可能地减小电介质材料的厚度，并且使用具有高介电常数的电介质的介电材料，这增加了电容器电荷的值 电容器。 本发明的目的是消除电容器板之间的漏电流，使得电容器能够在顶板和底板之间保持高电压。

    Method to prevent dishing in damascene CMP process
    3.
    发明授权
    Method to prevent dishing in damascene CMP process 失效
    防止镶嵌CMP工艺中凹陷的方法

    公开(公告)号：US6069082A

    公开(公告)日：2000-05-30

    申请号：US170734

    申请日：1998-10-13

    申请人： Harianto Wong ,  John Leonard Sudijono

    发明人： Harianto Wong ,  John Leonard Sudijono

    IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/302

    CPC分类号： H01L21/3212 ,  H01L21/7684 ,  H01L21/76877

    摘要： A method of fabrication of a metal lines without dishing using damascene and chemical-mechanical polish processes. A Key feature is the hard cap layer that is only formed over the trench opening. The hard cap layer prevents dishing of the metal line and also allows faster CMP than blanket polish stop layers. The method includes forming a first dielectric layer having a first trench opening over a semiconductor structure. A metal layer is deposited in the first trench opening. The metal layer has a dimple. The metal layer is preferably composed of Al or Cu. A hard mask is formed having a first opening over the first trench opening. The first opening is at least partially over first trench opening. A hard cap layer (e.g., W or WSi.sub.x) is selectively deposited on the metal layer exposed in the first opening. The hard cap layer, the hard mask, and the metal layer are chemical-mechanical polished to completely remove the hard mask resulting in a metal line having a "dishing free" flat top surface. The chemical-mechanical polish rate of the hard cap is less than the rate of the metal layer.

    摘要翻译： 使用镶嵌和化学机械抛光工艺制造金属线而不进行凹陷的方法。 一个主要特征是仅在沟槽开口形成的硬覆盖层。 硬盖层防止金属线的凹陷，并且还允许比橡皮布抛光停止层更快的CMP。 该方法包括形成具有在半导体结构上开口的第一沟槽的第一介电层。 金属层沉积在第一沟槽开口中。 金属层有凹坑。 金属层优选由Al或Cu组成。 在第一沟槽开口上形成有第一开口的硬掩模。 第一开口至少部分地超过第一沟槽开口。 在第一开口中暴露的金属层上选择性地沉积硬覆盖层（例如W或WSix）。 硬盖层，硬掩模和金属层进行化学机械抛光，以完全去除硬掩模，从而形成具有“无凹槽”的平坦顶表面的金属线。 硬帽的化学机械抛光速率小于金属层的速率。

    Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate
    4.
    发明授权
    Method and apparatus for removing contaminants from the perimeter of a semiconductor substrate 失效
    从半导体衬底的周边去除污染物的方法和装置

    公开(公告)号：US06540841B1

    公开(公告)日：2003-04-01

    申请号：US09607284

    申请日：2000-06-30

    申请人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

    发明人： Sudipto Ranendra Roy ,  Subhash Gupta ,  Simon Chooi ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Paul Kwok Keung Ho

    IPC分类号： B08B700

    CPC分类号： B08B1/04 ,  B08B3/04

    摘要： A new method and apparatus is provided that can be applied to clean outer edges of semiconductor substrates. Under the first embodiment of the invention, a brush is mounted on the surface of the substrate around the periphery of the substrate, chemicals are fed to the surface that is being cleaned by means of a hollow core on which the cleaning brush is mounted. The surface that is being cleaned rotates at a relatively high speed thereby causing the chemicals that are deposited on this surface (by the brush) to remain in the edge of the surface. Under the second embodiment of the invention, a porous roller is mounted between a chemical reservoir and the surface that is being cleaned, the surface that is being cleaned rotates at a relatively high speed. The chemicals that are deposited by the interfacing porous roller onto the surface that is being cleaned therefore remain at the edge of this surface thereby causing optimum cleaning action of the edge of the surface. After contaminants have been removed in this manner from the surface, the surface can be further cleaned by applying DI water.

    摘要翻译： 提供了可用于清洁半导体衬底的外边缘的新方法和装置。 在本发明的第一实施例中，刷子安装在基板周围的基板的表面上，化学品通过其上安装有清洁刷的中空芯被供给到待清洁的表面。 待清洁的表面以相对高的速度旋转，从而使沉积在该表面（由刷子）上的化学物质残留在表面的边缘。 在本发明的第二实施例中，多孔辊安装在化学容器和待清洁的表面之间，待清洁的表面以相对较高的速度旋转。 因此，由界面多孔辊沉积在待清洗的表面上的化学物质保留在该表面的边缘，从而引起表面边缘的最佳清洁作用。 污染物以这种方式从表面除去后，可以通过加入去离子水进一步清洁表面。

    Method of copper transport prevention by a sputtered gettering layer on backside of wafer
    6.
    发明授权
    Method of copper transport prevention by a sputtered gettering layer on backside of wafer 有权
    通过晶片背面的溅射吸气层预防铜传输的方法

    公开(公告)号：US06358821B1

    公开(公告)日：2002-03-19

    申请号：US09619376

    申请日：2000-07-19

    申请人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

    发明人： Subhash Gupta ,  Simon Chooi ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Xu Yi ,  Yakub Aliyu ,  Mei Sheng Zhou ,  John Leonard Sudijono

    IPC分类号： H01L2122

    CPC分类号： H01L21/3221 ,  C23C14/165 ,  H01L21/2885

    摘要： A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, and aluminum-copper-silicon is sputtered on the backside of the wafer to form a layer of metal. The back side sputtered aluminum layer may be partially oxidized at low temperature to further decrease the copper penetration possibility and to also provide greater flexibility in subsequent copper interconnect related processing. Once the back side layer is in place, the wafer can be processed as usual. The sputtered back side aluminum layer can be removed during final backside grinding.

    摘要翻译： 一种防止半导体晶片上的铜传输的方法，包括以下步骤。 提供具有正面和背面的半导体晶片。 从包括铝，铝 - 铜，铝 - 硅和铝 - 铜 - 硅的组中选择的金属溅射在晶片的背面以形成一层金属。 背面溅射的铝层可以在低温下部分氧化，以进一步降低铜的渗透可能性，并且在随后的铜互连相关处理中也提供更大的灵活性。 一旦背面层就位，就可以照常处理晶片。 最后的背面研磨可以除去溅射的背面铝层。