公开(公告)号：US09082776B2

公开(公告)日：2015-07-14

申请号：US13594544

申请日：2012-08-24

申请人： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Yi-Wen Wu ,  Yu-Peng Tsai ,  Chia-Wei Tu ,  Chung-Shi Liu

发明人： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Yi-Wen Wu ,  Yu-Peng Tsai ,  Chia-Wei Tu ,  Chung-Shi Liu

IPC分类号： H01L23/52 ,  H01L21/44 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/56 ,  H01L21/566 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10126 ,  H01L2224/11831 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

摘要翻译： 半导体封装包括半导体衬底，覆盖半导体衬底的接触焊盘，覆盖接触焊盘的互连层，形成在接触焊盘和互连层之间的钝化层，覆盖在互连层上的凸起以及覆盖在该互连层上的保护层 互连层和钝化层并覆盖凸块的下部。 保护层包括弯曲表面区域。

公开(公告)号：US20140054764A1

公开(公告)日：2014-02-27

申请号：US13594544

申请日：2012-08-24

申请人： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Yi-Wen Wu ,  Yu-Peng Tsai ,  Chia-Wei Tu ,  Chung-Shi Liu

发明人： Wen-Hsiung Lu ,  Ming-Da Cheng ,  Yi-Wen Wu ,  Yu-Peng Tsai ,  Chia-Wei Tu ,  Chung-Shi Liu

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L21/56 ,  H01L21/566 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10126 ,  H01L2224/11831 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor package includes a semiconductor substrate, a contact pad overlying the semiconductor substrate, an interconnect layer overlying the contact pad, a passivation layer formed between the contact pad and the interconnect layer, a bump overlying the interconnect layer, and a protection layer overlying the interconnect layer and the passivation layer and covering a lower portion of the bump. The protection layer includes a curved surface region.

摘要翻译： 半导体封装包括半导体衬底，覆盖半导体衬底的接触焊盘，覆盖接触焊盘的互连层，形成在接触焊盘和互连层之间的钝化层，覆盖在互连层上的凸起以及覆盖在该互连层上的保护层 互连层和钝化层并覆盖凸块的下部。 保护层包括弯曲表面区域。

公开(公告)号：US08937388B2

公开(公告)日：2015-01-20

申请号：US13492285

申请日：2012-06-08

申请人： Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

发明人： Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

IPC分类号： H01L23/52

CPC分类号： H01L24/06 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06051 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01023 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

摘要翻译： 公开了用于半导体器件的晶片级封装（WLP）的方法和装置。 电路的接触焊盘可以通过后钝化互连（PPI）线和PPI焊盘连接到焊料凸块。 PPI垫可以包括中空部分和开口。 PPI垫可以与PPI线一起形成为一体。 PPI垫的中空部分可用于控制球安装过程中使用的焊剂量，以便任何额外量的焊剂可以从PPI焊盘的固体部分的开口逸出。 焊锡球可以直接安装到PPI焊盘，而不使用正常的WLP封装所需的任何下凸块金属（UBM）。

公开(公告)号：US20130328190A1

公开(公告)日：2013-12-12

申请号：US13492285

申请日：2012-06-08

申请人： Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

发明人： Yi-Wen Wu ,  Ming-Che Ho ,  Wen-Hsiung Lu ,  Chia-Wei Tu ,  Chung-Shi Liu

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L24/06 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02331 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05551 ,  H01L2224/05557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06051 ,  H01L2224/10145 ,  H01L2224/11334 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01023 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

公开(公告)号：US20130341800A1

公开(公告)日：2013-12-26

申请号：US13529179

申请日：2012-06-21

申请人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Wen-Hsiung Lu ,  Hsien-Wei Chen ,  Tsung-Fu Tsai

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Wen-Hsiung Lu ,  Hsien-Wei Chen ,  Tsung-Fu Tsai

IPC分类号： H01L21/78 ,  H01L23/522

CPC分类号： H01L23/3135 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/15 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/0502 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/05 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552

摘要： A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

摘要翻译： 一种方法包括在晶片的衬底上形成电连接器，并模制聚合物层，至少一部分电连接器模制在聚合物层中。 执行第一锯切步骤以在聚合物层中形成沟槽。 在第一锯切步骤之后，执行第二锯切步骤以将晶片看成多个模具。

公开(公告)号：US09196532B2

公开(公告)日：2015-11-24

申请号：US13529179

申请日：2012-06-21

申请人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Wen-Hsiung Lu ,  Hsien-Wei Chen ,  Tsung-Fu Tsai

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Wen-Hsiung Lu ,  Hsien-Wei Chen ,  Tsung-Fu Tsai

IPC分类号： H01L21/78 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3135 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/15 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/0502 ,  H01L2224/05022 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/14 ,  H01L2224/03 ,  H01L2224/05 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2224/05552

摘要： A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.

摘要翻译： 一种方法包括在晶片的衬底上形成电连接器，并模制聚合物层，至少一部分电连接器模制在聚合物层中。 执行第一锯切步骤以在聚合物层中形成沟槽。 在第一锯切步骤之后，执行第二锯切步骤以将晶片看成多个模具。

公开(公告)号：US08569886B2

公开(公告)日：2013-10-29

申请号：US13302551

申请日：2011-11-22

申请人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC分类号： H01L23/485 ,  H01L21/28

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

摘要翻译： 公开了晶片级封装（WLP）半导体器件的方法和装置。 再次分布层（RDL）形成在与导体表面上的导电焊盘接触的第一钝化层上。 RDL层位于第一钝化层的第一区域的顶部。 在具有开口的RDL层上形成第二钝化层以暴露RDL层，并且在第一钝化层上方。 在与暴露的RDL层接触的第二钝化层上形成凸块下金属化（UBM）层。 通过将焊球或其它连接器的外周突出到表面上来确定与第一区域不相交的第一钝化层的第二区域。

公开(公告)号：US20130087925A1

公开(公告)日：2013-04-11

申请号：US13253799

申请日：2011-10-05

申请人： Tsung-Fu Tsai ,  Chia-Wei Tu ,  Yian-Liang Kuo ,  Ru-Ying Huang

发明人： Tsung-Fu Tsai ,  Chia-Wei Tu ,  Yian-Liang Kuo ,  Ru-Ying Huang

IPC分类号： H01L23/48

CPC分类号： H01L24/14 ,  H01L23/522 ,  H01L23/562 ,  H01L23/585 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/10126 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/17517 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2924/01322 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： A chip includes a dummy connector disposed at a top surface of the chip. A seal ring encircles a region directly underlying the dummy connector, with the region overlapping the dummy connector.

摘要翻译： 芯片包括设置在芯片顶表面的虚拟连接器。 密封环围绕虚拟连接器下方的区域，区域与虚拟连接器重叠。

公开(公告)号：US09508617B2

公开(公告)日：2016-11-29

申请号：US13411193

申请日：2012-03-02

申请人： Shiang-Ruei Su ,  Liang-Chen Lin ,  Chia-Wei Tu

发明人： Shiang-Ruei Su ,  Liang-Chen Lin ,  Chia-Wei Tu

IPC分类号： H01L21/66 ,  G01R31/28

CPC分类号： G01R31/2856 ,  H01L21/4853 ,  H01L22/14 ,  H01L22/34 ,  H01L24/16 ,  H01L2224/16157 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test board includes a first chip mounting area, a first input area, a second input area, a first output area, and a second output area. The test board also includes a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern. The first conductive pattern electrically connects a first pin of the first input area and a first pin of the first chip mounting area. The second conductive pattern electrically connects a first pin of the second input area and a second pin of the first chip mounting area. The third conductive pattern electrically connects a first pin of the first output area and a third pin of the first chip mounting area. The fourth conductive pattern electrically connects a first pin of the second output area and a fourth pin of the first chip mounting area.

摘要翻译： 测试板包括第一芯片安装区域，第一输入区域，第二输入区域，第一输出区域和第二输出区域。 测试板还包括第一导电图案，第二导电图案，第三导电图案和第四导电图案。 第一导电图形电连接第一输入区域的第一引脚和第一芯片安装区域的第一引脚。 第二导电图形电连接第二输入区域的第一引脚和第一芯片安装区域的第二引脚。 第三导电图形电连接第一输出区域的第一引脚和第一芯片安装区域的第三引脚。 第四导电图形电连接第二输出区域的第一引脚和第一芯片安装区域的第四引脚。

公开(公告)号：US20130127052A1

公开(公告)日：2013-05-23

申请号：US13302551

申请日：2011-11-22

申请人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

发明人： Chia-Wei Tu ,  Yian-Liang Kuo ,  Tsung-Fu Tsai ,  Ru-Ying Huang ,  Ming-Song Sheu ,  Hsien-Wei Chen

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0555 ,  H01L2224/05552 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/01023 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

摘要翻译： 公开了晶片级封装（WLP）半导体器件的方法和装置。 再次分布层（RDL）形成在与导体表面上的导电焊盘接触的第一钝化层上。 RDL层位于第一钝化层的第一区域之上。 在具有开口的RDL层上形成第二钝化层以暴露RDL层，并且在第一钝化层上方。 在与暴露的RDL层接触的第二钝化层上形成凸块下金属化（UBM）层。 通过将焊球或其它连接器的外周突出到表面上来确定与第一区域不相交的第一钝化层的第二区域。