公开(公告)号：US20140159228A1

公开(公告)日：2014-06-12

申请号：US13707159

申请日：2012-12-06

申请人： Weng Hong Teh ,  Chia-Pin Chiu

发明人： Weng Hong Teh ,  Chia-Pin Chiu

IPC分类号： H01L21/56 ,  H01L23/522

CPC分类号： H01L24/25 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/2501 ,  H01L2224/2505 ,  H01L2224/2512 ,  H01L2224/255 ,  H01L2224/73209 ,  H01L2224/81005 ,  H01L2224/92133 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15747 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00

摘要： Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.

摘要翻译： 这里通常讨论的是包括骰子之间的高密度互连和用于制造和使用这些设备的技术的设备。 在一个或多个实施例中，器件可以包括无冲突构建层（BBUL）衬底，其包括至少部分地嵌入在BBUL衬底中的第一管芯，第一管芯包括第一多个高密度互连焊盘。 第二管芯可以至少部分地嵌入在BBUL衬底中，第二管芯包括第二多个高密度互连焊盘。 高密度互连元件可以嵌入在BBUL基板中，高密度互连元件包括电耦合到第一和第二多个高密度互连焊盘的第三多个高密度互连焊盘。

公开(公告)号：US20140091445A1

公开(公告)日：2014-04-03

申请号：US13631205

申请日：2012-09-28

申请人： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

发明人： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC分类号： H01L23/34 ,  H01L21/98 ,  H01L23/495

CPC分类号： H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

摘要： An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

摘要翻译： 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。

公开(公告)号：US08937382B2

公开(公告)日：2015-01-20

申请号：US13169162

申请日：2011-06-27

申请人： Weng Hong Teh ,  John S. Guzek

发明人： Weng Hong Teh ,  John S. Guzek

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

CPC分类号： H05K3/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/32245 ,  H01L2224/82001 ,  H01L2224/82002 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

摘要： The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

摘要翻译： 本公开涉及制造微电子器件封装的领域，更具体地说，涉及具有无谐振积聚层（BBUL）设计的微电子器件封装，其中至少一个次级器件设置在该厚度内（即z方向或 z-height）微电子器件封装的微电子器件。

公开(公告)号：US20140264830A1

公开(公告)日：2014-09-18

申请号：US13801859

申请日：2013-03-13

申请人： Weng Hong Teh ,  Emile Davies-Venn ,  Ebrahim Andideh ,  Digvijay A. Raorane ,  Daniel N. Sobieski

发明人： Weng Hong Teh ,  Emile Davies-Venn ,  Ebrahim Andideh ,  Digvijay A. Raorane ,  Daniel N. Sobieski

IPC分类号： H01L23/498

CPC分类号： H01L23/49822 ,  H01L21/76807 ,  H01L21/7681 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/19 ,  H01L2221/1026 ,  H01L2224/12105 ,  H01L2924/18162

摘要： Bumpless build-up layer (BBUL) semiconductor packages with ultra-thin dielectric layers are described. For example, an apparatus includes a semiconductor die including an integrated circuit having a plurality of external conductive bumps. A semiconductor package houses the semiconductor die. The semiconductor package includes a dielectric layer disposed above the plurality of external conductive bumps. A conductive via is disposed in the dielectric layer and coupled to one of the plurality of conductive bumps. A conductive line is disposed on the dielectric layer and coupled to the conductive via.

摘要翻译： 描述了具有超薄电介质层的无创积层（BBUL）半导体封装。 例如，一种装置包括具有多个外部导电凸块的集成电路的半导体管芯。 半导体封装容纳半导体管芯。 半导体封装包括设置在多个外部导电凸块上方的电介质层。 导电通孔设置在电介质层中并耦合到多个导电凸块之一。 导电线设置在电介质层上并耦合到导电通孔。

公开(公告)号：US20140083858A1

公开(公告)日：2014-03-27

申请号：US13624288

申请日：2012-09-21

申请人： Weng Hong Teh ,  Kevin Lin ,  Feras Eid ,  Qing Ma

发明人： Weng Hong Teh ,  Kevin Lin ,  Feras Eid ,  Qing Ma

IPC分类号： B01D43/00 ,  H05K3/30

CPC分类号： H05K1/0272 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1815 ,  H01L2924/18162 ,  H05K1/0212 ,  H05K1/185 ,  H05K3/0097 ,  H05K2201/097 ,  H05K2203/1536 ,  H05K2203/308 ,  Y10T29/4913

摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a microfluidic die to a package structure, wherein the microfluidic die comprises a plurality of asymmetric electrodes that may be coupled with signal pads disposed within the package structure.

摘要翻译： 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将微流体管芯附接到封装结构，其中微流体管芯包括可以与设置在封装结构内的信号焊盘耦合的多个不对称电极。

公开(公告)号：US20130270715A1

公开(公告)日：2013-10-17

申请号：US13996495

申请日：2011-12-15

申请人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

发明人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

IPC分类号： H01L23/48

CPC分类号： H01L24/09 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

公开(公告)号：US09224674B2

公开(公告)日：2015-12-29

申请号：US13996495

申请日：2011-12-15

申请人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

发明人： Pramod Malatkar ,  Weng Hong Teh ,  John S. Guzek ,  Robert L. Sankman

IPC分类号： H01L27/08 ,  H01L23/552 ,  H01L23/48 ,  H01L23/00

CPC分类号： H01L24/09 ,  H01L23/481 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/97 ,  H01L27/08 ,  H01L2224/04105 ,  H01L2224/08235 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

摘要： A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

摘要翻译： 描述了具有无冲击的模具 - 封装接口和制造方法的封装的半导体管芯。 例如，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中并且具有最上层的导电线，其中之一直接连接到衬底的导电通孔的最下层的导电通孔。 在另一示例中，半导体封装包括具有最外层导电通孔的焊盘侧的衬底。 半导体管芯被嵌入在衬底中，并且具有最上层的导电线，其上设置有导电通孔层。 导电线中的至少一个直接耦合到半导体管芯的导电通孔，该导电通孔直接连接到衬底的导电通路的最下层的导电通孔。

公开(公告)号：US20150217995A1

公开(公告)日：2015-08-06

申请号：US14129542

申请日：2013-09-27

申请人： Weng Hong TEH ,  Sarah K. HANEY ,  Chyi Hwang LIM ,  INTEL CORPORATION

发明人： Weng Hong Teh ,  Sarah K Haney ,  Chyi Hwang Lim

IPC分类号： B81C1/00 ,  B81B3/00

CPC分类号： B81C1/0015 ,  B81B3/0051 ,  B81B2207/015 ,  B81C1/00476 ,  B81C2203/0714 ,  B81C2203/0735 ,  B81C2203/0771 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/73267

摘要： A semiconductor package comprising a suspended beam portion including an arrangement of through-hole structures. In an embodiment, a first surface of the suspended beam portion includes edges each defining in part a respective through-hole of a plurality of through-holes extending between the first surface and a second surface. The first surface comprises a plurality of arm portions each located between a respective pair of edge-adjacent edges. The first surface comprises a plurality of node portions each located at a respective junction of three or more of the plurality of arm portions. In another embodiment, for each of the plurality of node portions, a respective total number of arm portions which join one another at the node portion is a number other than four, or two arm portions which join one another at the node portion have respective mid-lines which are oblique to one another.

摘要翻译： 一种半导体封装，包括包括通孔结构的布置的悬挂梁部分。 在一个实施例中，悬挂梁部分的第一表面包括边缘，每个边缘部分地限定在第一表面和第二表面之间延伸的多个通孔的相应通孔。 第一表面包括多个臂部分，每个臂部分位于相应的一对边缘相邻边缘之间。 第一表面包括多个节点部分，每个节点部分位于多个臂部分中的三个或更多个的相应接合处。 在另一个实施例中，对于多个节点部分中的每个节点部分，在节点部分处彼此连接的臂部分的相应总数是除四个之外的数量，或者在节点部分处彼此连接的两个臂部分分别具有中间 相互倾斜的线条

公开(公告)号：US08633551B1

公开(公告)日：2014-01-21

申请号：US13537573

申请日：2012-06-29

申请人： Weng Hong Teh ,  Kevin L. Lin ,  Feras Eid ,  Qing Ma

发明人： Weng Hong Teh ,  Kevin L. Lin ,  Feras Eid ,  Qing Ma

IPC分类号： H01L27/14

CPC分类号： H01L24/19 ,  H01H1/0036 ,  H01H59/0009 ,  H01L23/5382 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： A semiconductor package having a mechanical fuse therein and methods to form a semiconductor package having a mechanical fuse therein are described. For example, a semiconductor structure includes a semiconductor package. A semiconductor die is housed in the semiconductor package. A microelectromechanical system (MEMS) device is housed in the semiconductor package. The MEMS device has a suspended portion. A mechanical fuse is housed in the semiconductor package and either coupled to, or decoupled from, the suspended portion of the MEMS device.

摘要翻译： 描述了具有机械熔断器的半导体封装以及形成其中具有机械熔丝的半导体封装的方法。 例如，半导体结构包括半导体封装。 半导体管芯被容纳在半导体封装中。 微机电系统（MEMS）装置容纳在半导体封装中。 MEMS器件具有悬挂部分。 机械保险丝容纳在半导体封装中，并且耦合到MEMS器件的悬置部分或从MEMS器件的悬挂部分解耦。

公开(公告)号：US20140001583A1

公开(公告)日：2014-01-02

申请号：US13539444

申请日：2012-06-30

申请人： Weng Hong Teh ,  Zuoming Ming Zhao ,  Danny R. Singh

发明人： Weng Hong Teh ,  Zuoming Ming Zhao ,  Danny R. Singh

IPC分类号： H01L29/84 ,  H01L21/50

CPC分类号： B81B3/0005 ,  H01L24/19 ,  H01L29/84 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00

摘要： An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die; and at least one device within the build-up carrier disposed in an area void of a layer of patterned conductive material. A method and an apparatus including a computing device including a package including a microprocessor are also disclosed.

摘要翻译： 一种包括模具的装置，包括第一侧和相对的第二侧，包括具有限定模具的厚度的接触点和侧壁的装置侧; 耦合到管芯的第二侧的积聚载体，所述堆积载体包括导电材料和绝缘材料的多个交替层，其中所述导电材料层中的至少一个耦合到所述接触点之一 的死亡 并且所述积聚载体内的至少一个装置设置在无图案化的导电材料层的区域中。 还公开了包括包括包括微处理器的封装的计算装置的方法和装置。