摘要:
Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.
摘要:
Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.
摘要:
Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.
摘要:
Outer-loop power control methods and apparatus are disclosed. In an exemplary embodiment, a short-term block error rate is measured for a received signal, and a coarse adjustment to a target signal-to-interference ratio (SIR) is calculated as a function of the short-term block error rate, a target block error rate, and a first loop tuning parameter. In some embodiments, a fine adjustment to the target SIR is also calculated, as a function of a smoothed block error rate, the target block error rate, and a second loop tuning parameter. The coarse adjustment provides quick responsiveness to received block errors, while the fine adjustment moderates the coarse adjustments by accounting for a longer-term view of the received block error rate. The target SIR adjustments disclosed herein may be computed in each of several iterations of an outer-loop power control loop.
摘要:
A nanowire molecular sensor, and a molecular detection system, comprising a nanowire waveguide (30), a nanowire sidewall (51) functionalized in order to attach a molecule (54), and light emissive point sources (52), wherein the amount of light emitted at an end (53) of the waveguide is dependent of the amount of specific molecules attached to the sidewall of the nanowire. A method employing said sensor may be used for single cell detection and analysis.
摘要:
The present invention provides a substrate (1) with a bulk layer (3) and a buffer layer (4) having a thickness of less than 2 μm arranged on the bulk layer (3) for growth of a multitude of nanowires (2) oriented in the same direction on a surface (5) of the buffer layer (4). A nanowire structure, a nanowire light emitting diode comprising the substrate (1) and a production method for fabricating the nanowire structure is also provided. The production method utilizes non-epitaxial methods for forming the buffer layer (4).
摘要:
The present invention relates to providing layers of different thickness on vertical and horizontal surfaces (15, 20) of a vertical semiconductor device (1). In particular the invention relates to gate electrodes and the formation of precision layers (28) in semiconductor structures comprising a substrate (10) and an elongated structure (5) essentially standing up from the substrate. According to the method of the invention the vertical geometry of the device (1) is utilized in combination with either anisotropic deposition or anisotropic removal of deposited material to form vertical or horizontal layers of very high precision.
摘要:
The present invention provides a photodiode comprising a p-i-n or pn junction at least partly formed by first and second regions (2) made of semiconductor materials having opposite conductivity type, wherein the p-i-n or pn junction comprises a light absorption region (11) for generation of charge carriers from absorbed light. One section of the p-i-n or pn junction is comprises by one or more nanowires (7) that are spaced apart and arranged to collect charge carriers generated in the light absorption region (11). At least one low doped region (10) made of a low doped or intrinsic semiconductor material provided between the nanowires (7) and one of said first region (1) and said second region (2) enables custom made light absorption region and/or avalanche multiplication region of the active region (9).
摘要:
The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.
摘要:
The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.