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公开(公告)号：US20090096077A1
公开(公告)日：2009-04-16
申请号：US12216637
申请日：2008-07-09
CPC分类号： H01L23/3107 , H01L25/03 , H01L25/16 , H01L2225/0652 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.
摘要翻译： 提供包括载体和芯片的榫眼包装结构。 载体具有与顶表面相对的顶表面和下表面。 顶表面形成至少一个榫头突起，并且下表面形成对应于形状，尺寸和位置的榫头突起的榫槽，使得两个载体可以通过将榫头投影连接到彼此并且彼此连接 相应的榫槽。 榫头和榫槽分别具有导电部分。 当榫头突起和榫槽彼此接合时，导电部分彼此电连接。 至少一个芯片嵌入在载体中。 芯片分别具有有源表面和背面，并与载体的顶表面和下表面电连接。
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公开(公告)号：US07964949B2
公开(公告)日：2011-06-21
申请号：US12216637
申请日：2008-07-09
IPC分类号： H01L23/02
CPC分类号： H01L23/3107 , H01L25/03 , H01L25/16 , H01L2225/0652 , H01L2225/06555 , H01L2225/06586 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A tenon-and-mortise packaging structure including a carrier and a chip is provided. The carrier has a top surface and a lower surface opposite to the top surface. The top surface forms at least one tenon projection, and the lower surface forms a mortise slot corresponding to the tenon projection in shape, size, and position, so that two carriers can be stacked on and jointed to each other by coupling the tenon projection to the corresponding mortise slot. The tenon projection and the mortise slot have conduction portions, respectively. When the tenon projection and the mortise slot are engaged with each other, the conduction portions are electrically connected with each other. At least one chip is embedded in the carrier. The chip has an active surface and a back side respectively and electrically connected with the top and the lower surfaces of the carrier.
摘要翻译： 提供包括载体和芯片的榫眼包装结构。 载体具有与顶表面相对的顶表面和下表面。 顶表面形成至少一个榫头突起，并且下表面形成对应于形状，尺寸和位置的榫头突起的榫槽，使得两个载体可以通过将榫头投影连接到彼此并且彼此连接 相应的榫槽。 榫头和榫槽分别具有导电部分。 当榫头突起和榫槽彼此接合时，导电部分彼此电连接。 至少一个芯片嵌入在载体中。 芯片分别具有有源表面和背面，并与载体的顶表面和下表面电连接。
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公开(公告)号：US08368216B2
公开(公告)日：2013-02-05
申请号：US12872644
申请日：2010-08-31
IPC分类号： H01L23/538 , H01L21/60 , H01L23/488
CPC分类号： H01L21/6835 , H01L21/563 , H01L21/568 , H01L23/3114 , H01L24/27 , H01L25/0652 , H01L25/50 , H01L2224/1184 , H01L2224/131 , H01L2224/1329 , H01L2224/16145 , H01L2224/2784 , H01L2224/73104 , H01L2224/73204 , H01L2224/81005 , H01L2224/81801 , H01L2224/8185 , H01L2224/831 , H01L2225/06513 , H01L2924/15311 , H01L2924/15321 , H01L2924/014
摘要： The present invention relates to a semiconductor package having at least one first layer chip, a plurality of first metal bumps, at least one second layer chip and a package body. The first layer chip includes a first active surface upon which the first metal bumps are disposed and a plurality of first signal coupling pads disposed adjacent to the first active surface. The second layer chip is electrically connected to the first layer chip, and includes a second active surface that faces the first active surface and a plurality of second signal coupling pads. The second signal coupling pads are capacitively coupled to the first signal coupling pads so as to provide proximity communication between the first layer chip and the second layer chip. The package body encapsulates the first layer chip, the first metal bumps, and the second layer chip, and the first metal bumps are partially exposed.
摘要翻译： 本发明涉及具有至少一个第一层芯片，多个第一金属凸块，至少一个第二层芯片和封装体的半导体封装。 第一层芯片包括设置有第一金属凸块的第一有源表面和与第一有源表面相邻设置的多个第一信号耦合焊盘。 第二层芯片电连接到第一层芯片，并且包括面向第一有源表面的第二有源表面和多个第二信号耦合焊盘。 第二信号耦合焊盘电容耦合到第一信号耦合焊盘，以便提供第一层芯片和第二层芯片之间的接近通信。 封装体封装第一层芯片，第一金属凸块和第二层芯片，并且第一金属凸块部分地露出。
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公开(公告)号：US20110278739A1
公开(公告)日：2011-11-17
申请号：US12777442
申请日：2010-05-11
IPC分类号： H01L23/52
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/48 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L2224/05571 , H01L2224/05573 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2225/0651 , H01L2225/06513 , H01L2225/06531 , H01L2225/06541 , H01L2225/06548 , H01L2225/06568 , H01L2225/06572 , H01L2924/00014 , H01L2924/10253 , H01L2924/1815 , H01L2924/19104 , H01L2924/19105 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased.
摘要翻译： 本发明涉及半导体封装。 半导体封装包括衬底，第一芯片和插入器。 第一芯片机械地和电连接到基板。 插入器的一些信号焊盘电容耦合到第一芯片的一些信号焊盘，以便在第一芯片和插入器之间提供接近通信。 由此，电容耦合的信号焊盘可以以细间距制成，因此半导体封装的尺寸减小，信号焊盘的密度增加。
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公开(公告)号：US07980757B2
公开(公告)日：2011-07-19
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译： 提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。 测量装置包括加热平台，加热滑板和固定支架。 加热平台具有第一加热区域和第一可更换夹具。 基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。 加热滑板具有第二加热区域和第二可更换夹具。 第二加热区域用于加热模塑料，第二可更换夹具具有容纳模塑料的空腔。 固定支架用于将加热滑板固定在加热平台上。
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公开(公告)号：US20090175312A1
公开(公告)日：2009-07-09
申请号：US12350643
申请日：2009-01-08
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
IPC分类号： G01N3/00
CPC分类号： G01N19/04
摘要： A bonding strength measuring device for measuring the bonding strength between a substrate and a molding compound disposed on the substrate is provided. The measuring device includes a heating platform, a heating slide plate, and a fixing bracket. The heating platform has a first heating area and a first replaceable fixture. The substrate is disposed on the first heating area, and the first replaceable fixture is used to fix the substrate and has an opening exposing the molding compound. The heating slide plate has a second heating area and a second replaceable fixture. The second heating area is used to heat the molding compound, and the second replaceable fixture has a cavity for accommodating the molding compound. The fixing bracket is used to fix the heating slide plate above the heating platform.
摘要翻译： 提供了用于测量基板和设置在基板上的模塑料之间的接合强度的接合强度测量装置。 测量装置包括加热平台，加热滑板和固定支架。 加热平台具有第一加热区域和第一可更换夹具。 基板设置在第一加热区域上，并且第一可更换夹具用于固定基板，并具有露出模塑料的开口。 加热滑板具有第二加热区域和第二可更换夹具。 第二加热区域用于加热模塑料，第二可更换夹具具有用于容纳模塑料的空腔。 固定支架用于将加热滑板固定在加热平台上。
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7.发明授权Semiconductor device package having a jumper chip and method of fabricating the same 有权具有跳线芯片的半导体器件封装及其制造方法公开(公告)号：US08222726B2
公开(公告)日：2012-07-17
申请号：US12748843
申请日：2010-03-29
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3121 , H01L23/48 , H01L24/05 , H01L24/17 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/83 , H01L25/0652 , H01L2224/0401 , H01L2224/13099 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/48599 , H01L2224/4899 , H01L2224/49175 , H01L2224/838 , H01L2225/0651 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/014 , H01L2924/0781 , H01L2924/07811 , H01L2924/10253 , H01L2924/15157 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device package and a method of fabricating the same are provided. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively.
摘要翻译： 提供半导体器件封装及其制造方法。 半导体器件封装包括衬底，第一芯片，跳线芯片，多个第一接合线和多个第二接合线。 衬底具有多个接触焊盘。 第一芯片通过第一接合线布置并电连接到基板。 跳线芯片设置在第一芯片上并且具有多个金属焊盘。 每个金属焊盘分别经由两个第二接合线电连接到衬底的两个接触焊盘。
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公开(公告)号：US20090051048A1
公开(公告)日：2009-02-26
申请号：US12222610
申请日：2008-08-13
申请人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
发明人： Yi-Shao Lai , Tsung-Yueh Tsai , Hsiao-Chuan Chang
CPC分类号： H01L24/32 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/91 , H01L2224/05571 , H01L2224/05573 , H01L2224/13099 , H01L2224/16225 , H01L2224/27013 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73257 , H01L2224/73265 , H01L2224/81136 , H01L2224/81192 , H01L2224/81801 , H01L2224/83051 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01082 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/181 , H01L2224/78 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A package structure and a manufacturing method thereof are provided. The package structure includes a carrier, a chip-bonding structure and a chip. The chip-bonding structure is formed on a first surface of the carrier. The chip-bonding structure includes a cavity, a dam, several via holes and several solder bumps. The solder bumps are received in the via holes and are correspond to the first connecting pads located on the carrier. The chip is embedded in the cavity of the chip-bonding structure. An active surface of the chip is tightly pasted on the first surface of the chip-bonding structure, and the first solder pads form electrical contact with the corresponding solder bumps. The chip of the package structure is precisely disposed on the carrier, not only simplifying the manufacturing process but also forming stable electrical connection between the chip and the carrier of the package structure.
摘要翻译： 提供一种封装结构及其制造方法。 封装结构包括载体，芯片结合结构和芯片。 芯片接合结构形成在载体的第一表面上。 芯片结合结构包括空腔，坝，几个通孔和几个焊料凸块。 焊料凸块被容纳在通孔中并且对应于位于载体上的第一连接焊盘。 芯片嵌入在芯片结合结构的空腔中。 芯片的有源表面被牢固地粘贴在芯片接合结构的第一表面上，并且第一焊盘与相应的焊料凸块形成电接触。 封装结构的芯片精确地布置在载体上，不仅简化了制造工艺，而且还在封装结构的芯片和载体之间形成稳定的电连接。
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9.发明申请ADVANCED QUAD FLAT NON-LEADED PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开先进的四边平面非引线封装结构及其制造方法公开(公告)号：US20120119342A1
公开(公告)日：2012-05-17
申请号：US12944695
申请日：2010-11-11
申请人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
发明人： Pao-Huei Chang Chien , Ping-Cheng Hu , Po-Shing Chiang , Wei-Lun Cheng , Hsueh-Te Wang , Hsiao-Chuan Chang , Tsung-Yueh Tsai , Yi-Shao Lai , Ping-Feng Yang
IPC分类号： H01L23/495 , H01L21/58 , H01L21/56
CPC分类号： H01L21/4832 , H01L21/561 , H01L23/3107 , H01L23/49503 , H01L23/49548 , H01L23/49582 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/97 , H01L2224/32245 , H01L2224/32257 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/4911 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/181 , H01L2924/19107 , H01L2924/30107 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads are designed to possess incurved sidewalls for enhancing the adhesion between the inner leads and the surrounding molding compound.
摘要翻译： 先进的四边形扁平无铅封装结构包括载体，芯片，多根导线和模塑料。 载体包括管芯焊盘和多个引线。 引线的内引线被设计成具有弯曲的侧壁，用于增强内引线和周围模塑料之间的粘附。
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公开(公告)号：US20120091575A1
公开(公告)日：2012-04-19
申请号：US12905756
申请日：2010-10-15
CPC分类号： H01L23/48 , H01L24/02 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L24/83 , H01L25/0657 , H01L2224/02371 , H01L2224/02381 , H01L2224/0401 , H01L2224/14155 , H01L2224/16225 , H01L2224/2919 , H01L2224/2929 , H01L2224/29294 , H01L2224/293 , H01L2224/32105 , H01L2224/32145 , H01L2224/32225 , H01L2224/33183 , H01L2224/73103 , H01L2224/73203 , H01L2224/81191 , H01L2224/83192 , H01L2224/83815 , H01L2224/83851 , H01L2224/83903 , H01L2225/06517 , H01L2225/06531 , H01L2225/06551 , H01L2225/06555 , H01L2924/014 , H01L2924/00012
摘要： The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap between the first signal coupling pads of the first chip and the second signal coupling pads of the second chip is controlled by the thickness of the dielectric layer. Therefore, the mass-production yield of the semiconductor package is increased.
摘要翻译： 半导体封装及其制造方法技术领域本发明涉及半导体封装及其制造方法。 半导体封装包括衬底，至少一个第一芯片，电介质层和至少一个第二芯片。 第一芯片被附接并电连接到基板。 第一芯片包括第一有源表面和多个第一信号耦合焊盘。 第一信号耦合焊盘设置成与第一有源表面相邻。 电介质层设置在第一有源表面上。 第二芯片通过金属凸块附接和电连接到基板。 第二芯片包括第二有源表面和多个第二信号耦合焊盘。 第二活性表面接触电介质层。 第二信号耦合焊盘设置成与第二有源表面相邻，并且电容耦合到第一芯片的第一信号耦合焊盘，以便提供第一芯片和第二芯片之间的接近通信。 由此，第一芯片的第一信号耦合焊盘与第二芯片的第二信号耦合焊盘之间的间隙由电介质层的厚度来控制。 因此，半导体封装的批量生产量增加。
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