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    Transistor with reduced parasitic capacitance
    2.
    发明授权
    Transistor with reduced parasitic capacitance 有权
    降低寄生电容的晶体管

    公开(公告)号：US08809962B2

    公开(公告)日：2014-08-19

    申请号：US13218988

    申请日：2011-08-26

    Applicant: Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

    Inventor： Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

    IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

    CPC classification number: H01L29/6653 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628

    Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.

    Abstract translation: 具有减小的寄生电容的可缩放晶体管通过用SiO 2或低k电介质侧壁间隔物代替高k电介质侧壁间隔物而形成。 实施例包括晶体管，其包括与替代金属栅电极间隔开的沟槽硅化物层，以及位于替代金属栅电极的面对沟槽硅化物层的侧表面上的SiO 2或低k材料层。 实施方法可以包括形成包括具有氮化物间隔物的可移除栅极的中间结构，去除可移除栅极，在氮化物间隔物上形成高k材料层，在高k材料上形成金属氮化物层，填充开口 用绝缘材料，然后去除其一部分以形成凹槽，去除金属氮化物层和高k材料层，沉积SiO 2或低k材料层，并在剩余的凹槽中形成替换金属栅极。

    Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material
    3.
    发明申请
    Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material 审中-公开
    通过在Si / Ge半导体材料中引入稳定物质来稳定PFET晶体管中的金属硅化物

    公开(公告)号：US20120241816A1

    公开(公告)日：2012-09-27

    申请号：US13052772

    申请日：2011-03-21

    Applicant: Stefan Flachowsky ,  Thilo Scheiper ,  Peter Javorka

    Inventor： Stefan Flachowsky ,  Thilo Scheiper ,  Peter Javorka

    IPC: H01L29/772 ,  H01L21/336

    CPC classification number: H01L21/26506 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    Abstract: When forming sophisticated P-channel transistors, the metal silicide agglomeration in a germanium-containing strain-inducing semiconductor alloy may be avoided or at least significantly reduced by incorporating a carbon and/or nitrogen species in a highly controllable manner. In some illustrative embodiments, the carbon species or nitrogen species is incorporated during the epitaxial growth process so as to form a surface layer of the strain-inducing semiconductor alloy with a desired nitrogen and/or carbon concentration and with a desired thickness without unduly affecting any other device areas.

    Abstract translation: 当形成复杂的P沟道晶体管时，通过以高度可控的方式并入碳和/或氮物质，可以避免含锗应变诱导半导体合金中的金属硅化物附聚或至少显着降低。 在一些说明性实施例中，在外延生长过程中引入碳物质或氮物质，以便形成具有所需氮和/或碳浓度并具有所需厚度的应变诱导半导体合金的表面层，而不会过度影响任何 其他设备区域。

    TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE
    5.
    发明申请
    TRANSISTOR WITH REDUCED PARASITIC CAPACITANCE 有权
    具有降低PARASIIC电容的晶体管

    公开(公告)号：US20130049142A1

    公开(公告)日：2013-02-28

    申请号：US13218988

    申请日：2011-08-26

    Applicant: Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

    Inventor： Yanxiang Liu ,  Jinping Liu ,  Min Dai ,  Xiaodong Yang

    IPC: H01L29/78 ,  H01L21/336

    CPC classification number: H01L29/6653 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628

    Abstract: Scaled transistors with reduced parasitic capacitance are formed by replacing a high-k dielectric sidewall spacer with a SiO2 or low-k dielectric sidewall spacer. Embodiments include transistors comprising a trench silicide layer spaced apart from a replacement metal gate electrode, and a layer of SiO2 or low-k material on a side surface of the replacement metal gate electrode facing the trench silicide layer. Implementing methodologies may include forming an intermediate structure comprising a removable gate with nitride spacers, removing the removable gate, forming a layer of high-k material on the nitride spacers, forming a layer of metal nitride on the high-k material, filling the opening with insulating material and then removing a portion thereof to form a recess, removing the metal nitride layers and layers of high-k material, depositing a layer of SiO2 or low-k material, and forming a replacement metal gate in the remaining recess.

    Abstract translation: 具有减小的寄生电容的可缩放晶体管通过用SiO 2或低k电介质侧壁间隔物代替高k电介质侧壁间隔物而形成。 实施例包括晶体管，其包括与替代金属栅电极间隔开的沟槽硅化物层，以及位于替代金属栅电极的面对沟槽硅化物层的侧表面上的SiO 2或低k材料层。 实施方法可以包括形成包括具有氮化物间隔物的可移除栅极的中间结构，去除可移除栅极，在氮化物间隔物上形成高k材料层，在高k材料上形成金属氮化物层，填充开口 用绝缘材料，然后去除其一部分以形成凹槽，去除金属氮化物层和高k材料层，沉积SiO 2或低k材料层，并在剩余的凹槽中形成替换金属栅极。

    Shrinkage of Critical Dimensions in a Semiconductor Device by Selective Growth of a Mask Material
    6.
    发明申请
    Shrinkage of Critical Dimensions in a Semiconductor Device by Selective Growth of a Mask Material 有权
    通过掩模材料的选择性增长在半导体器件中的临界尺寸的收缩

    公开(公告)号：US20120244710A1

    公开(公告)日：2012-09-27

    申请号：US13069488

    申请日：2011-03-23

    Applicant: Dmytro Chumakov ,  Volker Grimm

    Inventor： Dmytro Chumakov ,  Volker Grimm

    IPC: H01L21/311

    CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816

    Abstract: In sophisticated semiconductor devices, manufacturing techniques and etch masks may be formed on the basis of a mask layer stack which comprises an additional mask layer, which may receive an opening on the basis of lithography techniques. Thereafter, the width of the mask opening may be reduced by applying a selective deposition or growth process, which thus results in a highly uniform and well-controllable adjustment of the target width of the etch mask prior to performing the actual patterning process, for instance for forming sophisticated contact openings, via openings and the like.

    Abstract translation: 在复杂的半导体器件中，可以基于掩模层堆叠形成制造技术和蚀刻掩模，掩模层堆叠包括附加的掩模层，其可以基于光刻技术接收开口。 此后，可以通过施加选择性沉积或生长工艺来减小掩模开口的宽度，从而在执行实际图案化工艺之前导致对蚀刻掩模的目标宽度的高度均匀和良好可控的调整，例如 用于形成复杂的接触开口，通孔等。

    Prevention of fin erosion for semiconductor devices
    7.
    发明授权
    Prevention of fin erosion for semiconductor devices 有权
    防止半导体器件的翅片侵蚀

    公开(公告)号：US09190487B2

    公开(公告)日：2015-11-17

    申请号：US14283409

    申请日：2014-05-21

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

    Abstract translation: 在形成一次性栅极结构之前，介电金属化合物衬垫可沉积在半导体鳍片上。 介电金属复合衬里在一​​次性栅极结构和栅极间隔物的图案期间保护半导体鳍片。 在形成源极和漏极区域和替换栅极结构之前，可以去除电介质金属化合物衬垫。 或者，介电金属化合物衬垫可以沉积在半导体鳍片和栅极叠层上，并且可以在形成栅极间隔物之后被去除。 此外，可以在半导体鳍片和一次性栅极结构上沉积电介质金属化合物衬垫，并且可以在形成栅极间隔物和去除一次性栅极结构之后被去除。 在各实施例中，介电金属化合物衬垫可以在形成栅极间隔物期间保护半导体鳍片。

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