公开(公告)号：EP3214648A1

公开(公告)日：2017-09-06

申请号：EP16843627.7

申请日：2016-09-06

申请人： Shenzhen Goodix Technology Co., Ltd.

发明人： LIU, Yuping ,  LONG, Wei

IPC分类号： H01L23/495 ,  H01L23/488 ,  G01D5/12

CPC分类号： H01L23/562 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/488 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48479 ,  H01L2224/48499 ,  H01L2224/49433 ,  H01L2924/10161 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/20751

摘要： A sensor chip package assembly and an electronic device having the sensor chip package assembly are disclosed, where the sensor chip package assembly includes: a metal substrate (100) which has a bonding pad region (11) and a placement region (12), the bonding pad region having a plurality of metal bonding pads (13); a sensor chip (200) which is located on an upper surface of the metal substrate, and the sensor chip having a plurality of sensor chip bonding pads (21); an electrical connection assembly (300) which electrically connects a metal bonding pad and a sensor chip bonding pad; and a packaging material cover (400) which covers the metal substrate, the sensor chip and the electrical connection assembly, where any two adjacent metal bonding pads are spaced in an insulated manner by the packaging material cover. The sensor chip package assembly has advantages of a short development period and small warpage, thus improving efficiency of subsequent assembly while saving cost. In addition, since a plurality of metal bonding pads are independent from each other on a metal substrate, independent transmission of a plurality of signals between a sensor chip and the metal substrate may be realized, thus dramatically reducing risk of interference among the plurality of signals.

摘要翻译： 本发明公开了一种传感器芯片封装组件以及具有该传感器芯片封装组件的电子装置，其中传感器芯片封装组件包括：具有接合焊盘区域（11）和放置区域（12）的金属基板（100），该 接合焊盘区域，其具有多个金属接合焊盘（13）; 位于所述金属基板的上表面的传感器芯片（200），所述传感器芯片具有多个传感器芯片接合用焊盘（21）。 电连接组件（300），其电连接金属键合焊盘和传感器芯片键合焊盘; 以及覆盖所述金属基板，所述传感器芯片和所述电连接组件的封装材料盖（400），其中任意两个相邻的金属焊垫通过所述封装材料盖绝缘隔开。 传感器芯片封装组件具有开发周期短，翘曲小的优点，从而提高后续组装的效率，同时节约成本。 另外，由于多个金属接合焊盘在金属基板上彼此独立，因此可以实现传感器芯片与金属基板之间的多个信号的独立传输，从而显着降低了多个信号之间的干扰风险 。

公开(公告)号：EP2755235B1

公开(公告)日：2017-09-06

申请号：EP12830624.8

申请日：2012-06-19

申请人： Hamamatsu Photonics K.K.

发明人： IKEYA Tomohiro ,  FUKUI Toshiyuki ,  SUZUKI Hisanori ,  MURAMATSU Masaharu

IPC分类号： H01L27/146 ,  H04N5/369 ,  H01L23/00

CPC分类号： H01L27/14636 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L27/14618 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

公开(公告)号：EP2722881B1

公开(公告)日：2017-08-23

申请号：EP12290353.7

申请日：2012-10-17

申请人： Ampleon Netherlands B.V.

发明人： Bouisse, Gerard

IPC分类号： H01L23/64 ,  H01L23/66

CPC分类号： H01L27/0641 ,  H01L23/645 ,  H01L23/66 ,  H01L24/45 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2223/6655 ,  H01L2224/45015 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2224/45099 ,  H01L2924/00

摘要： A power transistor circuit uses first and second power transistors in differential mode. An inductor arrangement of inductors is formed by wire bonds between the drains. The transistors are in a mirrored configuration, and the inductor arrangement comprises wire bonds which extend between the drain connections across the space between the mirrored transistors.

摘要翻译： 功率晶体管电路使用差分模式的第一和第二功率晶体管。 电感器的电感器布置通过漏极之间的接线形成。 晶体管处于镜像配置，并且电感器装置包括在跨越镜像晶体管之间的空间的漏极连接之间延伸的引线键合。

公开(公告)号：EP3029167A4

公开(公告)日：2017-08-09

申请号：EP15819755

申请日：2015-05-20

申请人： NIPPON STEEL & SUMIKIN MAT CO ,  NIPPON MICROMETAL CORP

发明人： OYAMADA TETSUYA ,  UNO TOMOHIRO ,  DEAI HIROYUKI ,  ODA DAIZO

IPC分类号： H01L23/49 ,  C22C5/06 ,  C22F1/00 ,  C22F1/14

CPC分类号： H01L24/45 ,  C22C5/10 ,  H01L24/05 ,  H01L24/43 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05624 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45015 ,  H01L2224/45101 ,  H01L2224/45105 ,  H01L2224/45109 ,  H01L2224/45117 ,  H01L2224/45138 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45163 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48479 ,  H01L2224/48507 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/85439 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/181 ,  H01L2924/01001 ,  H01L2924/01007 ,  H01L2924/01049 ,  H01L2924/01031 ,  H01L2924/01048 ,  H01L2924/01028 ,  H01L2924/01005 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01004 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01203 ,  H01L2924/01044 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2224/48471 ,  H01L2924/00015 ,  H01L2924/01008 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/01033 ,  H01L2224/4554

摘要： The present invention provides a bonding wire which can satisfy bonding reliability, spring performance, and chip damage performance required in high-density packaging. A bonding wire contains one or more of In, Ga, and Cd for a total of 0.05 to 5 at%, and a balance being made up of Ag and incidental impurities.

摘要翻译： 本发明提供一种能够满足高密度封装所需的接合可靠性，弹簧性能和芯片损伤性能的接合线。 接合线包含总计0.05-5原子％的In，Ga和Cd中的一种或多种，​​余量由Ag和不可避免的杂质组成。

公开(公告)号：EP3186830A1

公开(公告)日：2017-07-05

申请号：EP15734328.6

申请日：2015-06-29

申请人： Heraeus Deutschland GmbH & Co. KG

发明人： KIM, Ki Ho ,  TARK, Yong -Deok ,  KANG, Il Tae ,  KIM, Byoung Gil ,  KIM, Tae Yeop

IPC分类号： H01L23/49

CPC分类号： H01L24/43 ,  H01B1/02 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/78301 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01045 ,  H01L2924/0102 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/013 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/01049 ,  H01L2924/01005 ,  H01L2224/05599

摘要： A bonding wire and a method of manufacturing the bonding wire are provided. The bonding wire contains 90.0 to 99.0 wt % of silver (Ag); 0.2 to 2.0 wt % of gold (Au); 0.2 to 4.0 wt % of palladium (Pd), platinum (Pt), rhodium (Rh), or a combination thereof; 10 to 1000 ppm of dopants; and inevitable impurities. In the wire, the ratio of (a)/(b) is 3 to 5, in which (a) represents the amount of crystal grains having orientation in crystalline orientations in a wire lengthwise direction and (b) represents the amount of crystal grains having orientation in crystalline orientations in the wire lengthwise direction.

摘要翻译： 提供了一种接合线和一种制造该接合线的方法。 接合线包含90.0〜99.0重量％的银（Ag） 金（Au）0.2〜2.0重量％。 钯（Pd），铂（Pt）或铑（Rh）或其组合的0.2至4.0重量％ 10至1000ppm的掺杂剂; （a）/（b）的比例为3〜5的不可避免的杂质。（a）是指在线材长度方向上晶体取向<100>取向的晶粒量， ）是指在导线长度方向上晶体取向<111>取向的晶粒的量。

公开(公告)号：EP1081757B8

公开(公告)日：2017-06-07

申请号：EP00118199

申请日：2000-08-31

申请人： S3 GRAPHICS CO LTD

发明人： YOUNG I KWON

IPC分类号： H01L23/31 ,  H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L25/04

CPC分类号： H01L22/20 ,  H01L23/3128 ,  H01L23/544 ,  H01L24/48 ,  H01L2223/54473 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

公开(公告)号：EP3086362A4

公开(公告)日：2017-05-31

申请号：EP15866377

申请日：2015-06-05

申请人： NIPPON MICROMETAL CORP ,  NIPPON STEEL & SUMIKIN MAT CO

发明人： ODA DAIZO ,  ETO MOTOKI ,  YAMADA TAKASHI ,  HAIBARA TERUO ,  OISHI RYO ,  UNO TOMOHIRO ,  OYAMADA TETSUYA

IPC分类号： H01L23/49 ,  C22C9/00 ,  C22F1/08 ,  H01L21/60

CPC分类号： H01L24/45 ,  C22C9/00 ,  C22F1/08 ,  H01L24/05 ,  H01L24/43 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/05624 ,  H01L2224/4312 ,  H01L2224/43125 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/45 ,  H01L2224/45005 ,  H01L2224/45015 ,  H01L2224/45109 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45609 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48011 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/85045 ,  H01L2224/85054 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2224/8509 ,  H01L2224/85203 ,  H01L2224/85439 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/20111 ,  H01L2924/20752 ,  H01L2924/01204 ,  H01L2924/01049 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/01001 ,  H01L2924/01007 ,  H01L2924/20105 ,  H01L2924/20656 ,  H01L2924/00 ,  H01L2924/2011 ,  H01L2924/01004 ,  H01L2924/01033

摘要： There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices. The bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, and the bonding wire contains In of 0.011 to 1.2% by mass and has the Pd coating layer of a thickness of 0.015 to 0.150 µm. With this configuration, it is able to increase the bonding longevity of a ball bonded part in a high-temperature and high-humidity environment, and thus to improve the bonding reliability. When the Cu alloy core material contains one or more elements of Pt, Pd, Rh and Ni in an amount, for each element, of 0.05 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 175°C or more. When an Au skin layer is further formed on a surface of the Pd coating layer, wedge bondability improves.

摘要翻译： 提供一种在其表面上具有Pd涂层的Cu接合线，其提高了球接合部在高温高湿环境下的接合可靠性，并且适用于车载装置。 本发明的半导体装置用接合线具备Cu合金芯材和在该Cu合金芯材的表面形成的Pd被覆层，该接合线含有0.011〜1.2质量％的In，并且具有 厚度为0.015至0.150μm。 利用该构造，能够增加球接合部在高温高湿环境下的接合寿命，并由此改善接合可靠性。 Cu合金芯材含有0.05〜1.2质量％的Pt，Pd，Rh和Ni中的一种或两种以上的元素时，能够提高球接合部的可靠性， 175°C或更高的温度环境。 当在Pd涂层的表面上进一步形成Au表层时，楔接合性提高。

公开(公告)号：EP3050101A4

公开(公告)日：2017-05-24

申请号：EP13894419

申请日：2013-09-27

申请人： INTEL CORP

发明人： ZHAO JUNFENG

IPC分类号： H01L25/00 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065

CPC分类号： H01L25/0657 ,  H01L21/50 ,  H01L21/565 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/96 ,  H01L25/00 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73217 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/92144 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/32225

摘要： A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

摘要翻译： 制造半导体器件的方法包括在第一和第二管芯上形成边缘。 轮缘横向延伸离开第一和第二骰子。 将第二模具堆叠在第一模具上，并且在堆叠之后通过边缘钻出一个或多个通孔。 该半导体器件包括在相应的第一和第二管芯以及对应的边缘中的至少一个上延伸的再分配层。 一个或多个通孔延伸穿过对应的边缘，并且一个或多个通孔通过边缘与第一和第二管芯连通。

公开(公告)号：EP3167482A1

公开(公告)日：2017-05-17

申请号：EP15721617.7

申请日：2015-04-28

申请人： Heraeus Deutschland GmbH & Co. KG

发明人： MILKE, Eugen ,  AINOUZ, Larbi ,  PRENOSIL, Peter

IPC分类号： H01L23/49 ,  C22C9/00 ,  C22F1/08 ,  H01B1/02

CPC分类号： H01B13/0006 ,  B21C1/02 ,  C22C9/00 ,  C22F1/008 ,  C22F1/08 ,  C23C30/005 ,  H01B1/026 ,  H01B13/0016 ,  H01B13/0036 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/4312 ,  H01L2224/4321 ,  H01L2224/4382 ,  H01L2224/43847 ,  H01L2224/43848 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45016 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/45664 ,  H01L2224/45666 ,  H01L2224/45669 ,  H01L2224/45671 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/85065 ,  H01L2224/85075 ,  H01L2924/00011 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/01204 ,  H01L2924/01001 ,  H01L2924/01007 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01005 ,  H01L2924/013 ,  H01L2924/00013 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/00

摘要： A process for manufacturing a bonding wire containing a core having a surface. The core contains ≧98.0% copper and has a cross sectional area of 75,00 to 600,000 μm2 and an elastic limit RP0.2 (yield strength) of 40 to 95 N/mm2. The process involves (a) providing a copper core precursor; (b) drawing the precursor until a final diameter of the wire core is reached; and (c) annealing the drawn wire at a minimum annealing temperature of 650 to 1000° C. through its entire cross section for a minimum annealing time of 4 seconds to 2 hours.

摘要翻译： 一种用于制造包括具有表面的芯的键合线的方法，其中芯包含≥98.0％的铜且横截面积在7500至600000μm2范围内，并且弹性极限RP0.2（屈服强度）为 该范围为40至95N / mm 2，该方法包括以下步骤：a）提供铜芯前体; b）拉伸前体直至达到线芯的最终直径; c）在650-1000℃范围内的最小退火温度下通过其整个横截面对退火丝进行退火，退火时间最短为4秒至2小时。

公开(公告)号：EP3158839A1

公开(公告)日：2017-04-26

申请号：EP15812624.3

申请日：2015-06-23

申请人： Zglue, Inc.

发明人： NASRULLAH, Jawad ,  ZHANG, Ming

IPC分类号： H05K7/14 ,  H05K1/14

CPC分类号： H01L22/34 ,  G06F17/5077 ,  H01L22/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/81136 ,  H01L2224/81193 ,  H01L2224/81908 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1531 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A system according to some examples herein includes a base chip which may include a plurality of attachment slots for attaching dies thereto. One or more of the attachment slots may be programmable attachment slots. The base chip may further include circuitry for interconnecting the dies attached to the base chip. For example, the base chip may include a plurality of cross bar switches, each of which is associated with respective ones of the plurality of attachment slots. The base chip may further include a configuration block, which is adapted to receive and transmit test signals for determining electrically connected signal lines of one or more attachment slots when one or more dies are attached to the base chip and which is further adapted to receive configuration data for programming signal (including power and ground) channels of the cross bar switches.

摘要翻译： 一种系统gemäß到在一些实施例中包括一个基片，其可包括附连槽的多个用于附连到其上。 一个或多个附连槽的可以是可编程的附连槽。 基底芯片还可以包括电路，其用于互连以便附接到基座芯片。 对于实施例，基底芯片可以包括横杆交换机的复数，每个的所有其与附接槽的多个respectivement者相关联。 基底芯片还可以包括一个配置块，所有这些是angepasst接收和发送一个或多个附连槽的确定性采矿电连接的信号线的测试信号。当一个或多个这些被连接到基座芯片和所有其进一步angepasst接收配置 用于编程信号（包括电源和地）横杆交换机的信道的数据。