公开(公告)号：EP1672970A3

公开(公告)日：2007-08-01

申请号：EP06003111.9

申请日：2000-10-10

Applicant: IBIDEN CO., LTD.

Inventor： Kawasaki, Yogo Ogaki-kojou, Ibiden Co., Ltd., ,  Sataki, Hiroaki Aoyagi-kojou, Ibiden Co., Ltd., ,  Iwata, Yukata Aoyagi-kojou, Ibiden Co., Ltd., ,  Tanabe, Tesuya Aoyagi-kojou, Ibiden Co., Ltd.,

IPC: H05K1/11 ,  H05K3/46

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/3457 ,  H05K3/381 ,  H05K3/382 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0796 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Through holes 36 are formed to penetrate a core substrate 30 and lower interlayer resin insulating layers 50, and via holes 66 are formed right on the through holes 36, respectively. Due to this, the through holes 36 and the via holes 66 are arranged linearly, thereby making it possible to shorten wiring length and to accelerate signal transmission speed. Also, since the through holes 36 and the via holes 66 to be connected to solder bumps 76 (conductive connection pins 78), respectively, are directly connected to one another, excellent reliability in connection is ensured.

公开(公告)号：EP1755073A3

公开(公告)日：2007-05-09

申请号：EP06119025.2

申请日：2006-08-16

Applicant: X-CYTE, Incorporated

Inventor： Cocita, Keith ,  Reis, Antonio, L.

IPC: G06K19/077

CPC classification number: G06K19/07745 ,  G06K19/07718 ,  G06K19/07749 ,  G06K19/07752 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/95085 ,  H01L2224/95122 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15165 ,  H05K3/242 ,  H05K3/246 ,  H05K3/32 ,  H05K2201/0347 ,  H05K2201/10727 ,  H05K2203/0723 ,  H05K2203/1545 ,  H01L2924/15153 ,  H01L2924/00

Abstract: A method of manufacturing RFID inlay structures includes providing a strap substrate containing an RFID chip. Strap pad patterns are formed adjacent said recessed regions over contacts of the RFID chip using a directly electroplateable resin (DER). The strap substrate is attached to an inlay substrate having an electrically conductive antenna and antenna contact patterns. The DER strap pad patterns, antenna pattern, antenna contacts and chip contacts are electroplated, thereby forming a metal interconnect between the contacts of the RFID chip and the antenna contacts on the inlay substrate. The strap substrate may be obtained from a web of strap substrates formed by a casting process. The DER material may be in the form of a DER ink and applied using a penplotter apparatus to form strap pad patterns or antenna coil patterns on the strap substrate, and to form antenna features and antenna contact patterns on the inlay substrate.

公开(公告)号：EP1494514A3

公开(公告)日：2007-04-18

申请号：EP04015390.0

申请日：2004-06-30

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Tanaka, Koichi

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K2201/0347 ,  H05K2201/09763 ,  H05K2203/1453 ,  H05K2203/171 ,  Y10T29/49098 ,  Y10T29/49099 ,  Y10T29/49155

Abstract: A wiring board (10) provided with a resistor comprises: an insulating substrate (11) having a surface; wiring patterns (14) formed on the surface, the wiring patterns (14) including first and second electrodes (14b,14c) spaced from each other by a certain distance; a first resistor (horizontal type resistor) (30) formed on the surface, the first resistor (30) having respective ends connected with the first and second electrodes (14b,14c), respectively; the wiring patterns (14) further including a third electrode (14a), occupying a first plane area on the surface; a second resistor (vertical type resistor) (16) formed on the third electrode (14a); a fourth electrode (18) formed on the second resistor (16); and the second resistor (16) and the fourth electrode (18) being located in a second plane area within the first plane area.

公开(公告)号：EP1755073A2

公开(公告)日：2007-02-21

申请号：EP06119025.2

申请日：2006-08-16

Applicant: X-CYTE, Incorporated

Inventor： Cocita, Keith ,  Reis, Antonio, L.

IPC: G06K19/077

CPC classification number: G06K19/07745 ,  G06K19/07718 ,  G06K19/07749 ,  G06K19/07752 ,  H01L24/95 ,  H01L25/50 ,  H01L2224/95085 ,  H01L2224/95122 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/0102 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15165 ,  H05K3/242 ,  H05K3/246 ,  H05K3/32 ,  H05K2201/0347 ,  H05K2201/10727 ,  H05K2203/0723 ,  H05K2203/1545 ,  H01L2924/15153 ,  H01L2924/00

Abstract: A method of manufacturing RFID inlay structures includes providing a strap substrate containing an RFID chip. Strap pad patterns are formed adjacent said recessed regions over contacts of the RFID chip using a directly electroplateable resin (DER). The strap substrate is attached to an inlay substrate having an electrically conductive antenna and antenna contact patterns. The DER strap pad patterns, antenna pattern, antenna contacts and chip contacts are electroplated, thereby forming a metal interconnect between the contacts of the RFID chip and the antenna contacts on the inlay substrate. The strap substrate may be obtained from a web of strap substrates formed by a casting process. The DER material may be in the form of a DER ink and applied using a penplotter apparatus to form strap pad patterns or antenna coil patterns on the strap substrate, and to form antenna features and antenna contact patterns on the inlay substrate.

Abstract translation: 制造RFID嵌体结构的方法包括提供包含RFID芯片的带基材。 使用可直接电镀树脂（DER）在RFID芯片的触点上形成邻近所述凹陷区域的绑带衬垫图案。 背带衬底连接到具有导电天线和天线接触图案的嵌体衬底。 DER绑带垫图案，天线图案，天线触点和芯片触点被电镀，由此在RFID芯片的触点与嵌体基板上的天线触点之间形成金属互连。 条带基底可以由通过铸造工艺形成的条带基底的网状物获得。 DER材料可以是DER油墨的形式并且使用笔式绘图仪设备施加以在带状基底上形成带状垫图案或天线线圈图案，并且在嵌入基底上形成天线特征和天线接触图案。

公开(公告)号：EP1713170A2

公开(公告)日：2006-10-18

申请号：EP06007600.7

申请日：2006-04-11

Applicant: FANUC LTD

Inventor： Odaka, SHunichi ,  Kariya, Isao, Rm. 6-303

IPC: H02N1/00

CPC classification number: H05K1/0254 ,  H02N1/004 ,  H05K3/244 ,  H05K3/246 ,  H05K2201/0347 ,  H05K2201/035 ,  H05K2201/098 ,  Y10T29/49002 ,  Y10T29/49009

Abstract: A method of production of electrodes for an electrostatic motor generating electrostatic force between a facing stator and slider, including forming core electrodes on a board of at least one of the stator and the slider by patterning a conductive substance and depositing a conductive substance on the core electrodes so that the side edges become rounded. Any method selected from electroplating, electroless plating, electrostatic coating, or screen printing can be used to deposit the conductive substance on the core electrodes. The core electrodes may be patterned using non-etching means. Further, electrodes for an electrostatic motor generating an electrostatic force between a facing stator and slider provided with core electrodes patterned on the board of at least one of the stator and the slider and a conductive substance deposited on the core electrodes to form deposition layers so that the side edges become rounded.

Abstract translation: 生产电极的用于在静电马达产生面向定子和滑动件之间的静电力，其中包括在所述定子的至少一个的板以及通过对所述芯图案化的导电物质和沉积导电物质滑块形成芯电极的方法 电极所以没有侧边变得圆润。 从电镀，化学镀，静电涂装法，或丝网印刷中的任意方法可以被用来对导电电极芯沉积物质。 芯电极可以使用非蚀刻装置来形成图案。 此外，电极，用于在设置有图案化在所述定子的至少一个的板和滑块并沉积在芯电极的导电物质，以形成沉积层，从而做芯电极的面临定子和滑动件之间的静电力的静电马达产生 侧边缘变圆。

公开(公告)号：EP1225664B1

公开(公告)日：2006-10-11

申请号：EP01310914.5

申请日：2001-12-27

Applicant: ITT MANUFACTURING ENTERPRISES, INC.

Inventor： Gray, Ian James Stafford ,  Impay, John

IPC: H01R43/24 ,  H01R9/05

CPC classification number: H05K3/20 ,  H01R24/50 ,  H01R43/18 ,  H01R43/24 ,  H01R2103/00 ,  H05K1/0284 ,  H05K1/119 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2201/09809 ,  H05K2203/1476 ,  H05K2203/175 ,  Y10S439/931

公开(公告)号：EP1670075A2

公开(公告)日：2006-06-14

申请号：EP05026727.7

申请日：2005-12-07

Applicant: NGK SPARK PLUG CO., LTD

Inventor： Nagai, Makoto ,  Yada, Setsuo ,  Uchida, Atsushi

IPC: H01L33/00

CPC classification number: H05K1/183 ,  H01L33/486 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/32225 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/246 ,  H05K3/4614 ,  H05K3/4629 ,  H05K3/4697 ,  H05K2201/0347 ,  H05K2201/09836 ,  H05K2201/09981 ,  H05K2201/10106 ,  H05K2203/061

Abstract: A wiring substrate for mounting a light emitting element, comprising: a substrate body comprising an insulating material and having a first surface and a back surface; and a cavity being opened into the first surface of said substrate body and having a mounting area for mounting a light emitting element at a bottom face of said cavity, wherein a metallized layer provided along a side face of said cavity and metallized layers provided in said substrate body are provided to continue to each other.

Abstract translation: 一种用于安装发光元件的布线基板，包括：基板主体，包括绝缘材料并具有第一表面和后表面; 并且一个空腔被打开到所述基片主体的第一表面中，并且具有用于将发光元件安装在所述空腔的底面的安装区域，其中沿着所述空腔的侧面设置的金属化层和设置在所述腔中的金属化层 衬底本体被设置成彼此连续。

公开(公告)号：EP1117283B1

公开(公告)日：2006-05-10

申请号：EP99943326.1

申请日：1999-09-14

Applicant: IBIDEN CO., LTD.

Inventor： EN, Honchin ,  NAKAI, Tohru ,  OKI, Takeo ,  HIROSE, Naohiro ,  NODA, Kouta

IPC: H05K3/18 ,  H05K3/46 ,  H05K1/09 ,  C25D5/18 ,  C23C18/34

CPC classification number: H05K3/4644 ,  C23C18/1607 ,  C23C18/1653 ,  C23C18/22 ,  C23C18/30 ,  C23C18/34 ,  C23C18/405 ,  C23C28/00 ,  C23C28/023 ,  C23C28/42 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/34 ,  C25D7/123 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/241 ,  H05K3/381 ,  H05K3/382 ,  H05K3/384 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4661 ,  H05K2201/0215 ,  H05K2201/0344 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0353 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1492 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method for manufacturing a printed wiring board having a high-density wiring and a highly-reliable connection between conductor layers even if the annealing process is omitted because a conductor circuit made of an electroplating layer excellent in crystallinity and uniform electrodepositability and formed on a base sheet and a via hole are provided. The method comprising forming an interlayer resin insulating layer on a conductor wiring forming board, making an opening for making a via hole in the interlayer resin insulating layer, forming an electroless plating layer (1008) on the interlayer resin insulating layer, applying a resist film (1003) to the layer (1008), forming an electroplating film thereon, removing the resist film, and removing the electroless plating layer by etching so as to form a conductor wiring and a via hole characterized in that the electroless plating layer (1008) serves as a cathode, the plating metal serves as an anode, and electroplating is performed intermittently while maintaining the voltage between the anode and cathode at a constant value.

Abstract translation: 即使省略退火处理，由于由结晶性和电沉积性均匀性优异的电镀层构成的导体电路形成于基体上，因此即使省略退火处理，也能够提供具有高密度布线和导体层间的可靠性高的连接的印刷布线板的制造方法 薄片和通孔。 该方法包括：在导体布线形成板上形成层间树脂绝缘层，在层间树脂绝缘层上形成用于形成通孔的开口，在层间树脂绝缘层上形成化学镀层（1008），将抗蚀剂膜 （1008），在其上形成电镀膜，去除抗蚀剂膜，并且通过蚀刻除去化学镀层，从而形成导体布线和通孔，其特征在于，无电镀层（1008） 用作阴极，电镀金属用作阳极，并且在将阳极和阴极之间的电压保持在恒定值的同时间歇地执行电镀。

公开(公告)号：EP1622435A1

公开(公告)日：2006-02-01

申请号：EP04090302.3

申请日：2004-07-28

Applicant: ATOTECH Deutschland GmbH

Inventor： Baron, David Thomas ,  Hofmann, Hannes-Peter ,  Schneider, Reinhard

IPC: H05K3/10 ,  H05K3/46 ,  H05K3/12 ,  H05K3/40 ,  H05K3/18 ,  H05K1/18

CPC classification number: H01L21/4867 ,  H01L21/486 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/185 ,  H05K3/107 ,  H05K3/125 ,  H05K3/1258 ,  H05K3/246 ,  H05K3/4069 ,  H05K3/465 ,  H05K3/4664 ,  H05K2201/0329 ,  H05K2201/0347 ,  H05K2201/09036 ,  H05K2203/013 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  H01L2924/00

Abstract: To create very small lines and spaces (≤ 25 µm, preferably ≤ 10 µm and being as low as 5 µm) on electronic circuit assemblies with justifiable effort a method is utilized which comprises the following method steps: a) providing a dielectric layer (5); b) forming a three-dimensional structure (10,10',10'') in the dielectric layer so as to provide one or more structure elements in the layer selected from the group comprising via holes, trenches and component recesses; c) applying a fluid (12) to at least part of surface regions of the dielectric layer exposed in the structure elements, the fluid containing or forming at least one of conductive particles or intrinsic conducting polymer on the surface; and d) metallizing (13) at least part of the surface regions.

Abstract translation: 为了在电子电路组件上以合理的努力创建非常小的线和空间（‰¤25μm，最好为‰¤10μm，最低为5μm），该方法包括以下方法步骤：a）提供介电层 （5）; b）在电介质层中形成三维结构（10,10'，10“），以便在选自包括通孔，沟槽和部件凹部的组中提供一个或多个结构元件; c）将流体（12）施加到暴露在结构元件中的介电层的表面区域的至少部分，所述流体包含或形成表面上的导电颗粒或本征导电聚合物中的至少一种; 和d）金属化（13）至少部分表面区域。

公开(公告)号：EP1568079A1

公开(公告)日：2005-08-31

申请号：EP03812777.5

申请日：2003-10-27

Applicant: INTEL CORPORATION

Inventor： GUZEK, John ,  AZIMI, Hamid ,  WOOD, Dustin ,  MOBLEY, Washington

IPC: H01L23/14 ,  H01L21/768 ,  H01L23/522 ,  H05K3/44 ,  H05K1/05

CPC classification number: H01L23/49827 ,  H01L23/142 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/056 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Apparatus and methods are provided for a rigid metal core carrier substrate. The metal core increases the modulus for elasticity of the carrier substrate to greater than 20 Gpa to better resist bending loads and stresses encountered during assembly, testing and consumer handling. The carrier substrate negates the need to provide external stiffening members resulting in a microelectronic package of reduced size and complexity. The coefficient of thermal expansion of the carrier substrate can be adapted to more closely match that of the microelectronic die, providing a device more resistant to thermally-induced stresses. In one embodiment of the method in accordance with the invention, a metal sheet having a thickness in the range including 200-500 µm and a flexural modulus of elasticity of at least 20 Gpa is laminated on both sides with dielectric and conductive materials using standard processing technologies to create a carrier substrate.

Abstract translation: 提供了用于刚性金属芯承载衬底的设备和方法。 金属芯将载体衬底的弹性模量增加到20Gpa以更好地抵抗在组装，测试和消费者处理期间遇到的弯曲载荷和应力。 载体衬底抵消了提供外部加强构件的需要，从而导致尺寸和复杂度减小的微电子封装。 载体衬底的热膨胀系数可以适合于更接近地匹配微电子管芯的热膨胀系数，从而提供更耐热致应力的器件。 在根据本发明的方法的一个实施例中，使用标准处理在厚度范围包括200-500μm和弹性弯曲模量至少20Gpa的金属板的两侧用电介质和导电材料层压 技术来创建载体基板。