摘要:
A process for bonding a silicon die to a package. This process comprises the following steps: (a) providing to the back surface of the die a barrier layer which is impervious to silicon; (b) providing to the barrier layer a layer of gold; and (c) bonding the die to the package by activating a binder composition disposed at the interface of the package and the layer of gold. The barrier layer prevents the migration of silicon to the gold layer, both at the time of application of the gold layer to the die and at the time of bonding the die to the package. Titanium and tungsten are preferred barrier layer materials, while the preferred binder composition is a gold-tin alloy solder. The prevention of silicon migration into the gold produces highly reliable bonds.
摘要:
Un procede de fixation d'une pastille IC (de circuit integre) de silicium (10) sur un substrat metallique de ceramique (38) consiste a revetir le dessous du de d'un materiau-barriere (32), tel que du chrome, puis a revetir la premiere couche d'un autre materiau (34) selectionne parmi le groupe constitue par l'argent, l'or, l'etain, l'antimoine, ou leurs alliages. Une preforme (36) de materiau selectionne parmi le groupe constitue par l'etain, l'etain avec une quantite relativement petite d'antimoine, ou l'etain avec une quantite relativement petite d'antimoine et de l'aluminium a l'etat de traces et ensuite placee sur le substrat chauffe (38) suivi du de (10) pour effectuer la fixation.
摘要:
Obtaining a semiconductor bonding structure body that has a superior stress alleviation property, and has a heat resistance property at the same time. A bonding structure body in which a semiconductor element (102) and an electrode (103) are bonded via a solder material, wherein a part (212) that allows bonding has a first intermetallic compound layer (207') that has been formed on the electrode side, a second intermetallic compound layer (208') that has been formed on the semiconductor element side, and a third layer (300) that is constituted by a phase (210) containing Sn and a sticks-like intermetallic compound part (209'), which is sandwiched between the two layers of the first intermetallic compound layer (207') and the second intermetallic compound layer (208'), and the sticks-like intermetallic compound part (209') is interlayer-bonded to both of the first intermetallic compound layer (207') and the second intermetallic compound layer (208').
摘要:
A semiconductor device (200, 300, 400) includes a semiconductor substrate (108, 208) in which a semiconductor element (150) is formed, an electrode structure (151, 202, 207) provided on a first surface (108d) of the semiconductor substrate (108, 208) to be electrically connected to the semiconductor element (150) and in which a first Al metal layer (105) composed of Al or Al alloy, a Cu diffusion-prevention layer (107) composed of e.g. Ti, TiN, TiW or W, a second Al metal layer (106) composed of Al or Al alloy and a Ni, Cu or Cu alloy layer (104) are formed in this order, and a conductive member (102) which is bonded to the electrode structure (151, 202, 207) via a sintered copper layer (103) disposed on a surface (104a) of the Ni, Cu or Cu alloy layer (104). In this semiconductor device, a crystal plane orientation of Al crystal grains on a surface (106a) of the second Al metal layer (106) is principally on the (110) plane. The semiconductor device (200) may comprise a second electrode structure (152) on the second surface (108e) of the semiconductor substrate (108), also formed of the layers (105), (107), (106) and (104) and bonded to a conductive member (102) via a sintered copper layer (103). Alternatively, the semiconductor device (300, 400) may comprise a plurality of semiconductor elements such as transistors, diodes and resistive elements formed on a semiconductor LSI chip (201, 205, 206) and a plurality of input/output electrode pads (202, 207) each formed of the layers (105), (107), (106) and (104). The LSI chip (201, 205, 206) may be bonded to another semiconductor LSI chip (205, 206), also having electrode pads (202, 207) formed of the layers (105), (107), (106) and (104), and/or to a conductive member (102) via a sintered copper layer (103).
摘要:
According to one embodiment, a semiconductor device (110) includes a semiconductor element (20), a mounting member (70) including Cu, and a bonding layer (50) provided between the semiconductor element (20) and the mounting member (70). The bonding layer (50) includes a first region (R1) including Ti and Cu, and a second region (R2) provided between the first region (R1) and the mounting member (70), and including Sn and Cu. A first position (P1) along the first direction is positioned between the semiconductor element (20) and a second position (P2) along the first direction. The first position (P1) is where the composition ratio (51r) of Ti in the first region (R1) is 0.1 times a maximum value (51x) of the composition ratio (51r) of Ti. The second position (P2) is where the composition ratio (52r) of Sn in the second region (R2) is 0.1 times a maximum value (52x) of the composition ratio (52r) of Sn. A distance (L1) between the first position (P1) and the second position (P2) is not less than 0.1 micrometres. According to another embodiment, a semiconductor device (120) includes a semiconductor element (20), a mounting member (70) including Cu, a first layer (41) provided between the semiconductor element (20) and the mounting member (70), the first layer (41) including Ti, a second layer (42) provided between the first layer (41) and the mounting member (70), the second layer (42) including Sn and Cu and a third layer (43) provided between the first layer (41) and the second layer (42), the third layer (43) including at least one selected from Ni, Pt, and Pd. In both embodiments, the semiconductor device (110, 120) is formed by bonding the semiconductor element (20) to the mounting member (70) by solid solution bonding. Thereby, a semiconductor device (110, 120) having good heat dissipation and high productivity can be provided.
摘要:
A silicon carbide semiconductor device 100 of the present invention includes: a silicon carbide layer 110; a reaction layer 120 which is in contact with the silicon carbide layer 110; a conductive oxidation layer 130 which is in contact with the reaction layer 120; and an electrode layer 140 which is formed over the reaction layer 120 with the conductive oxidation layer 130 interposed therebetween. It is preferable that a thickness of the conductive oxidation layer 130 falls within a range of 0.3nm to 2.25nm. According to the silicon carbide semiconductor device 100 of the present invention, by forming the electrode layer 140 over the reaction layer 120 with the conductive oxidation layer 130 interposed therebetween instead of directly forming the electrode layer 140 on the reaction layer 120, contact resistance between the semiconductor base body and the electrode layer can be further reduced. According to the silicon carbide semiconductor device 100 of the present invention, the thickness of the conductive oxidation layer 130 falls within a range of 0.3nm to 2.25nm and hence, the contact resistance between the semiconductor base body and the electrode layer can be still further reduced.
摘要:
A semiconductor device structure is disclosed that includes a wide-bandgap semiconductor portion selected from silicon carbide and the Group III nitrides. An interconnect structure (11) is made to the semiconductor portion (12), and the interconnect structure includes at least two diffusion barrier layers (13) alternating with two respective high electrical conductivity layers (14). The diffusion barrier layers have a coefficient of thermal expansion different from and lower than the coefficient of thermal expansion of the high electrical conductivity layers. The difference in the respective coefficients of thermal expansions are large enough to constrain the expansion of the high conductivity layers but less than a difference that would create a strain between adjacent layers that would exceed the bond strength between the layers.
摘要:
The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and a drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2μm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.