SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SAME
    38.
    发明公开
    SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD FOR PRODUCING SAME 有权
    碳化硅半导体元件及其制造方法

    公开(公告)号:EP2698808A1

    公开(公告)日:2014-02-19

    申请号:EP11863270.2

    申请日:2011-09-09

    发明人: OHNO, Jun-ichi

    IPC分类号: H01L21/28

    摘要: A silicon carbide semiconductor device 100 of the present invention includes: a silicon carbide layer 110; a reaction layer 120 which is in contact with the silicon carbide layer 110; a conductive oxidation layer 130 which is in contact with the reaction layer 120; and an electrode layer 140 which is formed over the reaction layer 120 with the conductive oxidation layer 130 interposed therebetween. It is preferable that a thickness of the conductive oxidation layer 130 falls within a range of 0.3nm to 2.25nm. According to the silicon carbide semiconductor device 100 of the present invention, by forming the electrode layer 140 over the reaction layer 120 with the conductive oxidation layer 130 interposed therebetween instead of directly forming the electrode layer 140 on the reaction layer 120, contact resistance between the semiconductor base body and the electrode layer can be further reduced. According to the silicon carbide semiconductor device 100 of the present invention, the thickness of the conductive oxidation layer 130 falls within a range of 0.3nm to 2.25nm and hence, the contact resistance between the semiconductor base body and the electrode layer can be still further reduced.

    LDMOS TRANSISTOR
    40.
    发明公开
    LDMOS TRANSISTOR 审中-公开
    LDMOS晶体管

    公开(公告)号:EP1915783A2

    公开(公告)日:2008-04-30

    申请号:EP06780280.1

    申请日:2006-08-02

    申请人: NXP B.V.

    摘要: The LDMOS transistor (1) of the invention comprises a substrate (2), a gate electrode (10), a substrate contact region (11), a source region (3), a channel region (4) and a drain region (5), which drain region (5) comprises a drain contact region (6) and a drain extension region (7). The drain contact region (6) is electrically connected to a top metal layer (23), which extends over the drain extension region (7), with a distance (723) between the top metal layer (23) and the drain extension region (7) that is larger than 2μm. This way the area of the drain contact region (6) may be reduced and the RF power output efficiency of the LDMOS transistor (1) increased. In another embodiment the source region (3) is electrically connected to the substrate contact region (11) via a suicide layer (32) instead of a first metal layer (21), thereby reducing the capacitive coupling between the source region (3) and the drain region (5) and hence increasing the RF power output efficiency of the LDMOS transistor (1) further.