公开(公告)号：EP2667409A1

公开(公告)日：2013-11-27

申请号：EP12168696.8

申请日：2012-05-21

申请人： NXP B.V.

发明人： Van der Heijden, Mark ,  Acar, Mustafa ,  Apostolidou, Melina ,  De Langen, Michel

IPC分类号： H01L23/66

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49052 ,  H01L2224/49096 ,  H01L2224/49097 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/2065 ,  H01L2924/20752 ,  H01L2924/30107 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2924/2076 ,  H01L2224/45099 ,  H01L2224/05599

摘要： An amplifier circuit is disclosed. The amplifier circuit comprises an amplifier IC (22); a control IC (24); a signal connections connected between the amplifier IC (22) and the control IC (24), the signal connections (44, 54) being adapted to communicate control signals between the control IC (24) and the amplifier IC (22); and a reference connections (42, 52) connected between the amplifier IC (22) and the control IC (24), the reference connections (42, 52) being adapted to communicate a reference voltage between the amplifier IC (22) and the control IC (24). The reference connections (42, 52) are substantially parallel to the signal connections (44 , 52). Both the reference connections (42, 52) and the signal connections (44, 54) are comprised of either wire or ribbon bonds.

摘要翻译： 公开了放大器电路。 放大器电路包括放大器IC（22）; 控制IC（24）; 连接在放大器IC（22）和控制IC（24）之间的信号连接，信号连接（44,54）适于在控制IC（24）和放大器IC（22）之间传送控制信号; 以及连接在所述放大器IC（22）和所述控制IC（24）之间的参考连接（42,52），所述参考连接（42,52）适于在所述放大器IC（22）和所述控制IC IC（24）。 参考连接（42,42）基本上平行于信号连接（44,45）。 参考连接（42,42）和信号连接（44,54）都由线或带状结合组成。

公开(公告)号：EP2380197A1

公开(公告)日：2011-10-26

申请号：EP09807470.1

申请日：2009-12-10

申请人： Freescale Semiconductor, Inc.

发明人： BOULAY, Jean Marie ,  GHANNAM, Ayad

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L23/64

CPC分类号： H01L23/5389 ,  H01L23/49844 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6644 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099

摘要： A high power semiconductor device for operation at powers greater than 5 watts for wireless applications comprises a semiconductor substrate including an active area of the high power semiconductor device, contact regions formed on the semiconductor substrate providing contacts to the active area of the high power semiconductor device, a dielectric layer formed over a part of the semiconductor substrate, a lead for providing an external connection to the high power semiconductor device and an impedance matching network formed on the semiconductor substrate between the active area of the high power semiconductor device and the lead. The impedance matching network includes conductor lines formed on the dielectric layer. The conductor lines are coupled to the contact regions for providing high power connections to the contact regions of the active area, and have a predetermined inductance for impedance matching.

摘要翻译： 在无线应用功率大于5瓦的用于外科手术的高功率半导体器件包括：半导体衬底包括在高功率半导体器件的有源区，形成在提供接触到高功率半导体器件的有源区中的半导体衬底的接触区域 中，形成在半导体衬底，引线的一部分，用于向高功率半导体器件的外部连接的提供和阻抗匹配网络形成在高功率半导体器件和引线的有源区之间的半导体衬底的介电层。 阻抗匹配网络包括形成在电介质层上的导体线。 导体线耦合到接触区域用于向所述有源区的接触区域提供高电源连接，并且具有用于阻抗匹配的预定电感。

公开(公告)号：EP1941578A4

公开(公告)日：2011-07-13

申请号：EP06825688

申请日：2006-10-06

申请人： NHEW R & D PTY LTD

发明人： WESTE NEIL H E

IPC分类号： H01P11/00 ,  H01Q1/00

CPC分类号： H01Q21/0093 ,  H01L23/48 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6677 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01Q1/2283 ,  H01Q7/00 ,  H01Q9/18 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method of forming the integrated circuit. The method includes, in an integrated circuit package, forming each bond to or from an integrated circuit pad that is intended to be an antenna connection to be elongated compared to other bonds, and arranged in an approximately perpendicular direction to the plane of the integrated circuit; encapsulating the top of the integrated circuit package with a dielectric material at a height greater than a desired antenna length; and milling the dielectric encapsulation down to a pre-selected and calibrated height, such that the elongated bond wire to/from the integrated circuit pad that is intended to be an antenna connection is severed, such that the approximately vertical bond wire to/from the integrated circuit pad that is intended to be an antenna connection forms a quarter wave monopole.

公开(公告)号：EP2159841A3

公开(公告)日：2011-04-27

申请号：EP09169228.5

申请日：2009-09-02

申请人： Linear Technology Corporation

发明人： Pruitt, David A.

IPC分类号： H01L25/07 ,  H01L23/64 ,  H01L23/495

CPC分类号： H01F19/08 ,  H01F38/14 ,  H01F2019/085 ,  H01F2027/2814 ,  H01L23/48 ,  H01L23/4952 ,  H01L23/642 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/072 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48491 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/4943 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48824

摘要： A semiconductor device is configured to provide current and voltage isolation inside an integrated circuit package. The semiconductor device includes first and second semiconductor dies, a first isolating block positioned on the first semiconductor die, and a second isolating block positioned on the second semiconductor die. The semiconductor device also includes a first interconnect coil having a plurality of wires connecting the first semiconductor die to the second isolating block, and a second interconnect coil having a plurality of wires connecting the second semiconductor die to the first isolating block.

摘要翻译： 半导体器件被配置为在集成电路封装内部提供电流和电压隔离。 该半导体器件包括第一和第二半导体管芯，位于第一半导体管芯上的第一隔离块以及位于第二半导体管芯上的第二隔离块。 该半导体器件还包括具有将第一半导体管芯连接到第二隔离块的多根导线的第一互连线圈以及具有将第二半导体管芯连接到第一隔离块的多条导线的第二互连线圈。

公开(公告)号：EP1941578A2

公开(公告)日：2008-07-09

申请号：EP06825688.2

申请日：2006-10-06

申请人： NHEW R&D Pty. Ltd.

发明人： WESTE, Neil, H.E.

IPC分类号： H01P11/00 ,  H01Q1/00

CPC分类号： H01Q21/0093 ,  H01L23/48 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6677 ,  H01L2224/05554 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49052 ,  H01L2224/49171 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01Q1/2283 ,  H01Q7/00 ,  H01Q9/18 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A method of forming the integrated circuit. The method includes, in an integrated circuit package, forming each bond to or from an integrated circuit pad that is intended to be an antenna connection to be elongated compared to other bonds, and arranged in an approximately perpendicular direction to the plane of the integrated circuit; encapsulating the top of the integrated circuit package with a dielectric material at a height greater than a desired antenna length; and milling the dielectric encapsulation down to a pre-selected and calibrated height, such that the elongated bond wire to/from the integrated circuit pad that is intended to be an antenna connection is severed, such that the approximately vertical bond wire to/from the integrated circuit pad that is intended to be an antenna connection forms a quarter wave monopole.

公开(公告)号：EP1683196A4

公开(公告)日：2007-03-21

申请号：EP04794597

申请日：2004-10-08

申请人： FREESCALE SEMICONDUCTOR INC

发明人： JOINER BENNETT A ,  ZHOU YAPING ,  HERBERG BEN W

IPC分类号： H01L23/50 ,  H01L20060101 ,  H01L23/48 ,  H01L23/552 ,  H01L23/66

CPC分类号： H01L23/552 ,  H01L23/50 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/49052 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor device has a die (10) overlying and electrically connected to a support structure (11), such as a substrate or a lead frame, via a plurality of interconnects. Aggressor interconnects (32, 38) are noise sources to victim interconnects (29, 59) carrying sensitive signals. An arrangement of shield interconnects (51-58) surround the victim interconnect (29, 59) in a cage-like structure to significantly block noise from the aggressor interconnect. In one form the shield interconnects are ground or power supply and the victim interconnect may be, for example, a clock signal or an RF signal. The number of shield interconnects and the number of protected victim interconnects varies depending upon design requirements. Either wire bonding or other interconnect technology (e.g. bump) is applicable.

公开(公告)号：EP0911874A2

公开(公告)日：1999-04-28

申请号：EP98120024.9

申请日：1998-10-22

申请人： NEC CORPORATION

发明人： Inaba, Takehito, c/o NEC Corporation

IPC分类号： H01L21/60 ,  H01L21/56

CPC分类号： H01L24/06 ,  H01L21/565 ,  H01L23/4951 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48599 ,  H01L2224/49052 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/20752 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399

摘要： In a semiconductor device, a bus bar (4a) is provided with a projection (9a). Based on a positional relationship between the projection and a metal wire (13a) subjected to the lateral deflection upon resin filling, the metal wire lateral deflection amount is managed. The projection may be provided on a suspension pin or at another portion of a lead frame. A cutout may be provided instead of the projection.

摘要翻译： 在半导体器件中，母线（4a）设置有突起（9a）。 基于树脂填充时突起与经受横向偏转的金属线（13a）之间的位置关系，管理金属线横向偏移量。 突起可以设置在悬挂销或引线框架的另一部分。 可以提供切口而不是突出部。

公开(公告)号：EP0194133A3

公开(公告)日：1987-04-01

申请号：EP86301528

申请日：1986-03-04

申请人： TEKTRONIX, INC.

发明人： Grellman, Erwin H. ,  Roland, Leonard A.

IPC分类号： H01L25/16 ,  H01L21/60 ,  H01L23/56

CPC分类号： H01L24/48 ,  H01L23/66 ,  H01L24/05 ,  H01L24/06 ,  H01L24/49 ,  H01L25/16 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/4554 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49174 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/1903 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  Y10T29/49124 ,  Y10T29/49162 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/85399

摘要： @ A bond wire connection between two semiconductor devices alleviates the problem of inductive loading at high frequencies by providing a capacitive effect which compensates for inductive reactance. The capacitive effect is provided by utilizing multiple parallel layers of bond wires at a common electrical connection point. As more layers are added the net impedance can be controlled so as to match the impedance driving the downstream semiconductor.

摘要翻译： 两个半导体器件之间的接合线连接通过提供补偿感抗的电容效应来缓解高频感应负载的问题。 通过在公共电连接点处利用多个平行的接合线层提供电容效应。 当增加更多的层时，可以控制净阻抗以匹配驱动下游半导体的阻抗。