公开(公告)号：EP1677582B1

公开(公告)日：2011-10-12

申请号：EP05027867.0

申请日：1996-12-19

Applicant: IBIDEN CO., LTD.

Inventor： Mori, Yoji Ibiden Co., Ltd. ,  Kawamura, Yoichiro Ibiden Co., Ltd.

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0201 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/0979 ,  H05K2201/09881 ,  Y10T29/49126 ,  Y10T428/24917

公开(公告)号：EP1856723A4

公开(公告)日：2010-08-04

申请号：EP06737501

申请日：2006-03-06

Applicant: SANMINA SCI CORP

Inventor： DUDNIKOV GEORGE JR

IPC: H05K3/42 ,  H05K1/02 ,  H05K1/16 ,  H05K3/18

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

公开(公告)号：EP2208542A1

公开(公告)日：2010-07-21

申请号：EP10000230.2

申请日：2010-01-12

Applicant: Bauer, Jörg R.

Inventor： Bauer, Jörg R.

IPC: B05D1/34 ,  B41J11/00 ,  B41J3/407 ,  B05D1/02

CPC classification number: B05D1/34 ,  B05D1/02 ,  B05D5/06 ,  B41J3/4073 ,  H05K3/125 ,  H05K3/1258 ,  H05K3/4664 ,  H05K2201/09881 ,  H05K2203/013

Abstract: Ein digitales Beschichtungssystem enthält wenigstens ein Auftragsbauteil 10 mit mehreren elektronisch ansteuerbaren Düsen 12 zum Abspritzen von Flüssigkeitströpfchen, eine Flüssigkeitsversorgungseinrichtung 50 zum Beschicken der Düsenflüssigkeit, eine Aufnahmeeinrichtung 26 zum Aufnehmen eines Gegenstandes 22 mit einer zu beschichtenden Oberfläche 24, eine Antriebseinrichtung 16, 28 zum Erzeugen einer Relativbewegung zwischen dem Auftragsbauteil und der Oberfläche und eine elektronische Steuereinrichtung 32, die geeignet ist, die Düsen und die Antriebseinrichtung derart zu steuern, dass zumindest auf Teilbereichen der Oberfläche nebeneinander und übereinander aufgebrachte Flüssigkeitströpfchen nach Erhärten der Flüssigkeit eine homogene Schicht 34 bilden.

Abstract translation: 该方法包括在表面（24）上喷涂热固化液滴，以产生预定厚度的层（d）。 喷雾液滴使得该层含有由热固性液体形成的预定厚度的层区域。 层区域与由与前者的热固性液体不同的另一热固性液体形成的另一预定厚度的层区域相邻。 包括以下独立权利要求：（1）具有具有涂层表面的基底的部件; 和（2）具有液体供应装置的数字涂层系统。

公开(公告)号：EP1677585A4

公开(公告)日：2010-05-19

申请号：EP05704388

申请日：2005-01-28

Applicant: IBIDEN CO LTD

Inventor： KARIYA TAKASHI ,  FURUTANI TOSHIKI

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/28 ,  H05K3/40

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/111 ,  H05K1/115 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09881 ,  H05K2201/10674 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multilayer printed wiring board 10 includes: a core substrate 20; a build-up layer 30 formed on the core substrate 20 and having a conductor pattern 32 on an upper surface; a low elastic modulus layer 40 formed on the build-up layer 30; lands 52 that are disposed on an upper surface of the low elastic modulus layer 40 and connected via solder bumps 66 to a semiconductor chip 70; and conductor posts 50 that are passing through the low elastic modulus layer 40 and electrically connecting lands 52 with conductor patterns 32. The conductor posts 50 are formed to have the diameters of an upper portion and a lower portion of 80µm, the diameter of an intermediate portion of 35µm, the height of 200µm, and the aspect ratio Rasp (height/minimum diameter) of 5.7 and the maximum diameter/minimum diameter of 2.3.

Abstract translation: 多层印刷线路板10包括：核心基板20; 形成在核心基板20上且在上表面上具有导体图案32的堆积层30; 形成在积层30上的低弹性模量层40; 设置在低弹性模量层40的上表面上并通过焊料凸点66连接到半导体芯片70的焊盘52; 以及导体柱50，该导体柱50穿过低弹性模量层40并且将平台52与导体图案32电连接。导体柱50被形成为具有80μm的上部和下部的直径，中间体的直径 部分为35μm，高度为200μm，长宽比Rasp（高度/最小直径）为5.7，最大直径/最小直径为2.3。

公开(公告)号：EP1768215A3

公开(公告)日：2009-10-21

申请号：EP06121218.9

申请日：2006-09-25

Applicant: Samsung SDI Co., Ltd.

Inventor： Kim, Chul-Hong c/o Legal & IP Team Samsung SDI Co. ,  Jung, Jin-Keun c/o Legal & IP Team Samsung SDI Co.

IPC: H01R12/08 ,  H01R12/16 ,  H05K3/36

CPC classification number: H05K3/323 ,  H01J2211/46 ,  H01R4/04 ,  H01R12/62 ,  H05K3/305 ,  H05K3/361 ,  H05K2201/09881 ,  H05K2203/1189

Abstract: The present invention relates to a plasma display panel which includes a plasma display panel, a driving circuit for driving the plasma display panel, an electrical signal transmitting wire for electrically connecting an electrode extended from the plasma display panel to the driving circuit, and an adhesive film interposed between the terminal end of the electrical signal transmitting wire and the terminal end of the electrode of the plasma display panel and electrically connecting between terminal ends. The adhesive film includes an anisotropic conductive film layer having a plurality of conductive particles and an insulated dummy at either or both ends of the anisotropic conductive film layer. Alternatively, the adhesive film may include a plurality of conductive particles with an insulated layer on each side.

公开(公告)号：EP2006909A9

公开(公告)日：2009-08-05

申请号：EP07745152.4

申请日：2007-06-13

Applicant: Panasonic Corporation

Inventor： TSUMURA, Tetsuya Panasonic Corporation ,  NISHIYAMA, Hiroharu Panasonic Corporation ,  TSUJIMOTO, Etsuo Panasonic Corporation

IPC: H01L23/36 ,  H01L23/12 ,  H05K1/02 ,  H05K3/06 ,  H05K3/08

CPC classification number: H05K3/202 ,  H01L23/3737 ,  H01L23/49861 ,  H01L24/81 ,  H01L2924/12042 ,  H01L2924/15747 ,  H05K1/0373 ,  H05K1/056 ,  H05K3/027 ,  H05K3/06 ,  H05K2201/0209 ,  H05K2201/0376 ,  H05K2201/09118 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A heat dissipating wiring board comprises: a metal wiring plate with a circuit pattern formed therein: a filler containing resin layer embedded with the metal wiring plate such that a top surface of the metal wiring plate is exposed; and a heat dissipating plate arranged on an under surface of the filler containing resin layer, wherein the circuit pattern is formed of a through groove provided in the metal wiring plate, and this through groove is made up of: a fine groove that opens at the top surface of the metal wiring plate; and an expanded groove that expands from a lower end of the fine groove toward the under surface of the metal wiring plate. The heat dissipating wiring board is capable of improving reliability against electric insulation due to a dust or the like in a space of the through groove.

公开(公告)号：EP1720392A3

公开(公告)日：2009-04-08

申请号：EP06017887.8

申请日：1996-03-29

Applicant: IBIDEN CO., LTD.

Inventor： Yasue, Toshihiko ,  Hiramatsu, Yasuji ,  Yano, Hideki ,  Ishitani, Yoshifumi ,  Kawamura, Yoichiro ,  Murase, Hideki ,  Suzuki, Ayumi ,  Kawade, Masato

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4661 ,  H05K3/0094 ,  H05K3/382 ,  H05K3/384 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0773

Abstract: It is to provide a multilayer printed circuit board having excellent resolution, interlaminar insulation property and resistance to cool-heat shock without forming unevenness on the surface and lowering peel strength even if the thickness of the resin insulating layer is thin. The invention proposes a multilayer printed circuit board comprising an upper conductor circuit layer (6), a lower conductor circuit layer (5) and a resin insulating layer (2,3) electrically insulating both the conductor circuit layers, in which the resin insulating layer is a composite layer comprised of an insulating layer (2) made from a heat-resistant resin hardly soluble in acid or oxidizing agent as a lower layer and an adhesive layer (3) for electroless plating made from a heat-resistant resin as an upper layer.

Abstract translation: 本发明提供一种即使树脂绝缘层的厚度薄，也不会在表面产生凹凸，剥离强度降低的，分辨率优良，层间绝缘性，耐冷热冲击性的多层印刷电路板。 本发明提出了一种多层印刷电路板，其包括上导体电路层（6），下导体电路层（5）和电绝缘两个导体电路层的树脂绝缘层（2,3），其中树脂绝缘层 是由作为下层的由难溶于酸或氧化剂的耐热树脂制成的绝缘层（2）和由耐热树脂制成的用于无电电镀的粘合剂层（3）作为上层 层。

公开(公告)号：EP1121008B1

公开(公告)日：2008-07-30

申请号：EP99933214.1

申请日：1999-07-30

Applicant: IBIDEN CO., LTD.

Inventor： HIROSE, Naohiro ,  NODA, Kouta ,  SEGAWA, Hiroshi ,  EN, Honjin ,  TSUKADA, Kiyotaka ,  ISHIDA, Naoto ,  ASANO, Kouji ,  SHOUDA, Atsushi

IPC: H05K3/46

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is made in a resin (20) with a laser to form a viahole. A copper foil (22) etched into a thin film (3 νm) to lower the heat conductivity is used as a conformal mask, thereby making an opening (20a) in the resin (20) by fewer times of irradiation with a pulse laser beam. This prevents formation of any undercut in the resin (20) on which an interlayer resin-insulating layer is to be formed, enabling improvement in the connection reliability of the viahole.

Abstract translation: 利用激光在树脂（20）中形成开口以形成通孔。 蚀刻成薄膜（3νm）以降低热导率的铜箔（22）用作共形掩模，由此通过用脉冲激光束照射较少次数来在树脂（20）中形成开口（20a） 。 这防止了在要形成层间树脂绝缘层的树脂20中形成任何底切，从而改善了通孔的连接可靠性。

公开(公告)号：EP1098558B1

公开(公告)日：2008-02-20

申请号：EP99926766.9

申请日：1999-06-23

Applicant: IBIDEN CO., LTD.

Inventor： NISHIWAKI, Yoko ,  NODA, Kouta

IPC: H05K3/46 ,  H05K3/38

CPC classification number: H05K3/4626 ,  H05K3/0023 ,  H05K3/0082 ,  H05K3/0094 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4602 ,  H05K2201/0108 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09881 ,  H05K2203/0278 ,  H05K2203/0307 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K2203/1157 ,  Y10T29/49155

Abstract: A multilayer printed wiring board which is constructed such that a conductor circuit (29) is formed on a core substrate (21) via an interlayer resin insulation layer (32), a through hole (23) is provided in the core substrate and a filler (25) is filled in the through hole. The interlayer resin insulation layer on the core substrate is flat and a roughened layer (31) of the same kind is formed on the entire surface including side surfaces of the conductor circuit on the core substrate. A cover plated layer (30) is formed directly above the through hole, a roughened layer is formed on the entire surfaces including side surfaces of this conductor layer and the conductor circuit located in the same layer of the conductor layer, and a flat-surface interlayer resin insulation layer for filling a recess between conductors is formed on the surface of this roughened layer, thereby providing an excellent crack resistance under such conditions as a heat cycle and eliminating a possible damage to the cover plated layer.

公开(公告)号：EP1856723A2

公开(公告)日：2007-11-21

申请号：EP06737501.4

申请日：2006-03-06

Applicant: Sanmina-SCI Corporation

Inventor： DUDNIKOV, George, Jr.

IPC: H01L21/311 ,  H01L23/48

CPC classification number: H05K3/429 ,  H05K1/0257 ,  H05K1/0259 ,  H05K1/116 ,  H05K1/167 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/0187 ,  H05K2201/0738 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09718 ,  H05K2201/09881 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49139 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielelectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.