公开(公告)号：US08237267B2

公开(公告)日：2012-08-07

申请号：US13023132

申请日：2011-02-08

申请人： Minoru Shinohara

发明人： Minoru Shinohara

IPC分类号： H01L23/34

CPC分类号： H01L23/49575 ,  H01L23/525 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/49107 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.

摘要翻译： 提供了半导体芯片堆叠在其上的半导体器件。 半导体器件的尺寸和厚度减小。 在第一存储器芯片和第二存储器芯片中，位于下级并由位于上级的第二存储器芯片隐藏的第一存储器芯片的第一焊盘由再布线引出，由此第一焊盘 暴露于第二存储芯片的第二存储芯片和第二存储器芯片的第二焊盘可以通过电线耦合在一起。 此外，在再布线上形成的微计算机芯片和第三焊盘通过第二存储器芯片上的导线耦合在一起，由此可以在没有间隔件介入的情况下完成层叠的存储器芯片的线耦合。

公开(公告)号：US20110156229A1

公开(公告)日：2011-06-30

申请号：US12978602

申请日：2010-12-26

申请人： Minoru SHINOHARA

发明人： Minoru SHINOHARA

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/49537 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.

摘要翻译： 提供了能够减小包括微型和功率MOSFET的半导体器件的尺寸的技术。 半导体器件通过单个封装其中形成有微结构的第一半导体芯片和在其中形成功率MOSFET的第二半导体芯片来获得。 与其中形成有微结构的第一半导体芯片和其中形成功率MOSFET的第二半导体芯片被分开封装的情况相比，可以减小半导体器件的尺寸。

公开(公告)号：US20110037170A1

公开(公告)日：2011-02-17

申请号：US12851618

申请日：2010-08-06

申请人： Minoru SHINOHARA

发明人： Minoru SHINOHARA

IPC分类号： H01L23/485 ,  H01L21/50

CPC分类号： H01L25/16 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/49861 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： Reduction of the size of and enhancement of the reliability, mounting strength, and mounting reliability of a semiconductor module are achieved. The semiconductor module includes: a wiring substrate; an electronic component placed over the upper surface of the wiring substrate; an electronic component placed over the under surface of the wiring substrate; a lead placed over the under surface of the wiring substrate; and encapsulation resin covering the under surface of the wiring substrate including the electronic component and the lead. The lead includes: a first portion coupled to an electrode pad via a joining material; a second portion bent from the first portion; and a third portion bent from the second portion. The third portion is positioned closer to the peripheral edge portion side of the under surface of the wiring substrate than the first portion. At the same time, the third portion is arranged at a position farther from the under surface of the wiring substrate than the first portion. The third portion of the lead is exposed from the main surface and side surface of the encapsulation resin and functions as a terminal for external coupling.

摘要翻译： 实现半导体模块的可靠性，安装强度和安装可靠性的减小和增强。 半导体模块包括：布线基板; 布置在所述布线基板的上表面上的电子部件; 布置在所述布线基板的下表面上的电子部件; 引线放置在布线基板的下表面之上; 以及覆盖包括电子部件和引线的布线基板的下表面的封装树脂。 引线包括：通过接合材料耦合到电极焊盘的第一部分; 从所述第一部分弯曲的第二部分; 以及从第二部分弯曲的第三部分。 第三部分比第一部分更靠近布线基板的下表面的周边部分侧。 同时，第三部分布置在比第一部分更远离布线基板的下表面的位置处。 引线的第三部分从封装树脂的主表面和侧表面露出，并用作用于外部耦合的端子。

公开(公告)号：US20100148350A1

公开(公告)日：2010-06-17

申请号：US12606504

申请日：2009-10-27

申请人： Minoru SHINOHARA ,  Tomibumi INOUE ,  Seiichiro TSUKUI

发明人： Minoru SHINOHARA ,  Tomibumi INOUE ,  Seiichiro TSUKUI

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.

摘要翻译： 在包括堆叠在作为下封装的第一半导体封装上的作为上封装的第二半导体封装的POP型半导体器件中，形成在第一半导体封装的第一布线基板上的多个主表面侧焊盘分布地布置在两者上 作为位于第一布线基板的主表面的中心部分的边界的芯片安装区域的侧面，从而允许采用直通成型方法。 因此，形成在第一半导体封装中的第一布线基板的主表面上的第一密封体作为下封装从第一布线基板的一个第二侧朝向相同基板的另一第二侧的中心部分延伸。

公开(公告)号：US20090200680A1

公开(公告)日：2009-08-13

申请号：US12365806

申请日：2009-02-04

申请人： Minoru SHINOHARA ,  Makoto Araki ,  Michiaki Sugiyama

发明人： Minoru SHINOHARA ,  Makoto Araki ,  Michiaki Sugiyama

IPC分类号： H01L23/48

CPC分类号： G06F1/185 ,  G11C5/02 ,  G11C5/063 ,  H01L23/5388 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

摘要翻译： 存储卡具有布线板，堆叠在布线板的主表面上的四个存储芯片，以及安装在最上层的存储芯片的表面上的控制器芯片和插入器。 存储芯片堆叠在布线板的表面上，使得它们的长边沿着与布线板的长边方向相同的方向。 最下层的存储芯片以错位的方式在朝向存储卡前端的方向上以预定的距离安装在布线板上，以便不与布线板的焊盘重叠。 堆叠在最下层的存储芯片上的三个存储芯片被布置成使得它们在其上形成焊盘的短边位于存储卡的前端。

公开(公告)号：US5847388A

公开(公告)日：1998-12-08

申请号：US872945

申请日：1997-06-11

申请人： Steven J. Foote ,  Minoru Shinohara

发明人： Steven J. Foote ,  Minoru Shinohara

IPC分类号： H01J37/252 ,  H01J37/244

CPC分类号： H01J37/244 ,  H01J2237/2442 ,  H01J2237/2555

摘要： A two-piece collimator for use in high takeoff angle energy dispersive spectroscopy (EDS) is provided. The two-piece collimator includes a base section and an extension section. The collimator base section may be attached rigidly to the end of an EDS detector tube. The collimator extension section is removably attached to and extends from the base section. Apertures through the base and extension sections are easily aligned with each other and with an EDS detector. The length of the collimator extension section is preferably selected such that the distal end of the extension section extends below the bottom of an upper pole piece of an electron microscope in which the collimator is employed. A two-piece collimator in accordance with the present invention effectively reduces stray radiation, including back scattered electrons, which may cause artifacts in a detected EDS X-ray spectrum. Alternatively, a collimator in accordance with the present invention may be used in combination with an existing pole piece insert collimation device by removing the extension section from the two-piece collimator.

摘要翻译： 提供了一种用于高起飞角能量色散光谱（EDS）的两件式准直器。 两件式准直器包括基部和延伸部。 准直器基部可以刚性地附接到EDS检测器管的端部。 准直器延伸部分可拆卸地附接到基部并从基部延伸。 通过基座和延伸部分的孔径可以很容易地与EDS检测器对准。 优选地选择准直器延伸部分的长度，使得延伸部分的远端延伸到其中使用准直器的电子显微镜的上极片的底部的下方。 根据本发明的两件式准直器有效地减少包含背散射电子的杂散辐射，这可能在检测到的EDS X射线光谱中引起伪影。 或者，根据本发明的准直器可以与现有的极片插入准直装置组合使用，通过从两件式准直器移除延伸部分。

公开(公告)号：US08779575B2

公开(公告)日：2014-07-15

申请号：US12978602

申请日：2010-12-26

申请人： Minoru Shinohara

发明人： Minoru Shinohara

IPC分类号： H01L23/48

CPC分类号： H01L23/49537 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.

摘要翻译： 提供了能够减小包括微型和功率MOSFET的半导体器件的尺寸的技术。 半导体器件通过单个封装其中形成有微结构的第一半导体芯片和在其中形成功率MOSFET的第二半导体芯片来获得。 与其中形成有微结构的第一半导体芯片和其中形成功率MOSFET的第二半导体芯片被分开封装的情况相比，可以减小半导体器件的尺寸。

公开(公告)号：US20080300020A1

公开(公告)日：2008-12-04

申请号：US12116956

申请日：2008-05-08

申请人： Hirotaka Nishizawa ,  Hideo Koike ,  Hironori Iwasaki ,  Junichiro Osako ,  Minoru Shinohara ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Hideo Koike ,  Hironori Iwasaki ,  Junichiro Osako ,  Minoru Shinohara ,  Tamaki Wada

IPC分类号： H04M1/00

CPC分类号： H04W8/20 ,  H04L63/0853 ,  H04W12/06

摘要： The loss of data stored in a secure memory card, such as a SIM card, due to the physical destruction thereof is prevented. A host unit performs card authentication of a memory card, and transmits update data for the memory card by security communication to update data when the result of the authentication is OK. Then, the host unit outputs a request for mirror-updating the card data to a base station server. When an access is permitted, the card data is transmitted to the base station server via the host unit to mirror-update the card data. When the mirror-updating of the card data is completed, the base station server returns a completion confirmation to the host unit, so that a data backup process is completed. By thus causing the base station server to mirror-update the data in the memory card, the loss of the stored data is prevented.

摘要翻译： 防止存储在安全存储卡（例如SIM卡）中的数据由于其物理破坏而丢失。 主机单元执行存储卡的卡认证，并且当认证结果正常时通过安全通信发送存储卡的更新数据以更新数据。 然后，主机单元向基站服务器输出镜像更新卡数据的请求。 当允许访问时，卡数据经由主机单元被发送到基站服务器以镜像更新卡数据。 当卡数据的镜像更新完成时，基站服务器向主机单元返回完成确认，从而完成数据备份处理。 通过使基站服务器对存储卡中的数据进行镜像更新，可以防止存储的数据的丢失。

公开(公告)号：US20070158440A1

公开(公告)日：2007-07-12

申请号：US11566985

申请日：2006-12-05

申请人： Hirotaka Nishizawa ,  Norihisa Yamamoto ,  Jun Miyake ,  Junichiro Osako ,  Minoru Shinohara ,  Tamaki Wada

发明人： Hirotaka Nishizawa ,  Norihisa Yamamoto ,  Jun Miyake ,  Junichiro Osako ,  Minoru Shinohara ,  Tamaki Wada

IPC分类号： G06K19/06

CPC分类号： G06K19/07745 ,  G06K19/077 ,  G06K19/07732 ,  G06K19/07733 ,  G06K19/07739 ,  H01L23/055 ,  H01L23/49838 ,  H01L23/49855 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L2224/05553 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device improved in IC card function is disclosed. An external connecting terminal for extended interface not conforming to ISO/IEC7816-3 is disposed on a first main surface of a card chip and in an area sandwiched in between two rows of external connecting terminals for interface conforming to ISO/IEC7816-3 which is for IC card function. With this layout, the memory card function and other electronic circuit functions can be incorporated into the card chip and hence it is possible to improve the function of the card chip.

摘要翻译： 公开了改进了IC卡功能的半导体器件。 用于扩展接口的不符合ISO / IEC7816-3的外部连接端子设置在卡芯片的第一主表面上，并且夹在两排用于符合ISO / IEC7816-3的接口的外部连接端子的区域中 用于IC卡功能。 通过这种布局，存储卡功能和其他电子电路功能可以并入卡片芯片中，因此可以提高卡片芯片的功能。

公开(公告)号：US08648453B2

公开(公告)日：2014-02-11

申请号：US12606504

申请日：2009-10-27

申请人： Minoru Shinohara ,  Tomibumi Inoue ,  Seiichiro Tsukui

发明人： Minoru Shinohara ,  Tomibumi Inoue ,  Seiichiro Tsukui

IPC分类号： H01L23/52 ,  H01L21/00

CPC分类号： H01L23/49816 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1076 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.

摘要翻译： 在包括堆叠在作为下封装的第一半导体封装上的作为上封装的第二半导体封装的POP型半导体器件中，形成在第一半导体封装的第一布线基板上的多个主表面侧焊盘分布地布置在两者上 作为位于第一布线基板的主表面的中心部分的边界的芯片安装区域的侧面，从而允许采用直通成型方法。 因此，形成在第一半导体封装中的第一布线基板的主表面上的第一密封体作为下封装从第一布线基板的一个第二侧朝向相同基板的另一第二侧的中心部分延伸。