公开(公告)号：US08637969B2

公开(公告)日：2014-01-28

申请号：US13908728

申请日：2013-06-03

Applicant: Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

Inventor： Teak-hoon Lee ,  Won-keun Kim ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/291 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/1811 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Abstract translation: 一种形成具有大容量和减小或最小化体积的半导体封装的方法包括：使用粘合剂层将半导体衬底附着在支撑衬底上，其中半导体衬底包括多个第一半导体芯片和切屑区域，其中 多个第一半导体芯片中的第一和第二半导体芯片通过芯片切割区域彼此分离，并且半导体衬底包括其上形成有源区域的第一表面和与第一表面相对的第二表面; 在所述多个第一半导体芯片中的第一和第二半导体芯片之间形成具有第一切口宽度的第一切割槽，使得半导体基板被分离成多个第一半导体芯片; 分别将对应于第一半导体芯片的多个第二半导体芯片附着到多个第一半导体芯片; 形成模塑层以填充第一切割槽; 以及在成形层中形成具有小于第一切口宽度的第二切口宽度的第二切割槽，以将模制层分离成覆盖多个第一半导体芯片中的一个的各个成型层和相应的一个 多个第二半导体芯片。

公开(公告)号：US08637350B2

公开(公告)日：2014-01-28

申请号：US13439447

申请日：2012-04-04

Applicant: Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

Inventor： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC: H01L21/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。

公开(公告)号：US20090045513A1

公开(公告)日：2009-02-19

申请号：US12193561

申请日：2008-08-18

Applicant: Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

Inventor： Pyoung-Wan KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Teak-Hoon LEE ,  Chul-Yong JANG

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Abstract translation: 一种包括半导体芯片的半导体芯片封装，所述半导体芯片包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。

公开(公告)号：US20120282735A1

公开(公告)日：2012-11-08

申请号：US13439447

申请日：2012-04-04

Applicant: Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

Inventor： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC: H01L21/82

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract translation: 一种制造芯片堆叠的半导体封装的方法，该方法包括制备包括多个通过硅通孔（TSV）的多个第一芯片的基底晶片; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。

公开(公告)号：US20120077311A1

公开(公告)日：2012-03-29

申请号：US13314464

申请日：2011-12-08

Applicant: Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

Inventor： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC: H01L21/60

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

Abstract translation: 在一个实施例中，半导体封装包括第一绝缘体和具有第一有源表面和与第一有源表面相对的第一后表面的第一半导体芯片。 第一半导体芯片设置在第一绝缘体内。 第一活性表面被第一绝缘体暴露。 第一后表面基本上被第一绝缘体包围。 半导体封装包括在第一绝缘体内并邻近第一半导体芯片的一侧的柱。

公开(公告)号：US08093703B2

公开(公告)日：2012-01-10

申请号：US12104333

申请日：2008-04-16

Applicant: Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

Inventor： Pyoung-Wan Kim ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC: H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/18 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

Abstract translation: 在一个实施例中，半导体封装包括第一绝缘体和具有第一有源表面和与第一有源表面相对的第一后表面的第一半导体芯片。 第一半导体芯片设置在第一绝缘体内。 第一活性表面被第一绝缘体暴露。 第一后表面基本上被第一绝缘体包围。 半导体封装包括在第一绝缘体内并邻近第一半导体芯片的一侧的柱。

公开(公告)号：US20090289359A1

公开(公告)日：2009-11-26

申请号：US12469253

申请日：2009-05-20

Applicant: Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

Inventor： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC: H01L23/498

CPC classification number: H01L23/49816 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 根据本发明总体构思的半导体封装可以包括其上形成有连接端子的一个表面的基底基板和具有覆盖基底基板的成型层的第一封装基板。 模制层面向连接端子的圆周，并且包括分别具有不同尺寸的圆周的第一表面和第二表面的侧表面。

公开(公告)号：US20140154839A1

公开(公告)日：2014-06-05

申请号：US14093853

申请日：2013-12-02

Applicant: Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

Inventor： Jung-seok Ahn ,  Dong-hyeon Jang ,  Ho-geon Song ,  Sung-jun Im ,  Chang-seong Jeon ,  Teak-hoon Lee ,  Sang-sick Park

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/92125 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Abstract translation: 一种制造芯片堆叠的半导体封装的方法，所述方法包括制备包括多个第一芯片的基片，每个第一芯片均具有穿硅通孔（TSV）; 将包括多个第一芯片的基底晶片接合到支撑载体; 准备多个第二芯片; 通过将所述多个第二芯片接合到所述多个第一芯片来形成堆叠的芯片; 用密封部分密封堆叠的芯片; 并将堆叠的芯片彼此分离。

公开(公告)号：US20130032947A1

公开(公告)日：2013-02-07

申请号：US13482415

申请日：2012-05-29

Applicant: Sang-sick Park ,  Tae-je Cho ,  Sang-wook Park ,  Teak-hoon Lee ,  Kwang-chul Choi ,  Myung-sung Kang

Inventor： Sang-sick Park ,  Tae-je Cho ,  Sang-wook Park ,  Teak-hoon Lee ,  Kwang-chul Choi ,  Myung-sung Kang

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/544 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor package that stably protects an internal semiconductor chip from external shocks, and a method of manufacturing the semiconductor package is disclosed. The semiconductor package includes a first semiconductor chip including a first body layer having a first surface, a second surface, and a lateral surface between the first surface and the second surface, and a first protective layer that exposes an edge portion of the first surface and forms a step difference with the first surface; an encapsulation structure that covers a lateral surface of the first body layer and the edge portion of the first surface so as to encapsulate the first semiconductor chip to have a locking structure; and a first conductive terminal formed on the first body layer through the protective layer.

Abstract translation: 公开了一种稳定地保护内部半导体芯片免受外部冲击的半导体封装以及半导体封装的制造方法。 该半导体封装包括第一半导体芯片，该第一半导体芯片包括具有第一表面，第二表面和第一表面与第二表面之间的侧表面的第一本体层，以及暴露第一表面的边缘部分的第一保护层和 与第一表面形成阶梯差; 封装结构，其覆盖第一主体层的侧面和第一表面的边缘部分，以便将第一半导体芯片封装成具有锁定结构; 以及通过保护层形成在第一主体层上的第一导电端子。

公开(公告)号：US08154122B2

公开(公告)日：2012-04-10

申请号：US12469253

申请日：2009-05-20

Applicant: Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

Inventor： Chul-Yong Jang ,  Pyoung-Wan Kim ,  Teak-Hoon Lee

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor package and a method of manufacturing the semiconductor package are provided. A semiconductor package according to the present general inventive concept may include a base substrate having one surface on which a connection terminal is formed and a first package substrate having a molding layer covering the base substrate. The molding layer faces a circumference of the connection terminal and includes a side surface having first and second surfaces having a circumference of a different size, respectively.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 根据本发明总体构思的半导体封装可以包括其上形成有连接端子的一个表面的基底基板和具有覆盖基底基板的成型层的第一封装基板。 模制层面向连接端子的圆周，并且包括分别具有不同尺寸的圆周的第一表面和第二表面的侧表面。