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    TECHNOLOGIES FOR SECURE ENCRYPTED EXTERNAL MEMORY FOR FIELD-PROGRAMMABLE GATE ARRAYS (FPGAS)
    2.
    发明申请
    TECHNOLOGIES FOR SECURE ENCRYPTED EXTERNAL MEMORY FOR FIELD-PROGRAMMABLE GATE ARRAYS (FPGAS) 审中-公开

    公开(公告)号：US20180150644A1

    公开(公告)日：2018-05-31

    申请号：US15721814

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Rahul Khanna ,  Susanne M. Balle ,  Francesc Guim Bernat ,  Sujoy Sen ,  Paul Dormitzer

    IPC: G06F21/62 ,  G06F21/76 ,  H04L9/08 ,  G06F13/16 ,  H03K19/173

    Abstract: Technologies for encrypted data access by field-programmable gate array (FPGA) user kernels include a computing device having an FPGA and an external memory device accessible by the FPGA. The FPGA includes a secure key store, a micro-encryption engine, and multiple slots for user kernels that are each identifiable with an index. A user kernel is programmed at an index and a symmetric encryption key is provisioned to the secure key store at the index. The micro encryption engine may read encrypted data from the external memory device, decrypt the encrypted data with the key associated with the index of the user kernel, and forward plain text data to the user kernel. The micro encryption engine may also receive plain text data from the user kernel, encrypt the plain text data with the key, and write the encrypted data to the external memory device. Other embodiments are described and claimed.

    TECHNOLOGIES FOR PRE-CONFIGURING ACCELERATORS BY PREDICTING BIT-STREAMS
    4.
    发明申请
    TECHNOLOGIES FOR PRE-CONFIGURING ACCELERATORS BY PREDICTING BIT-STREAMS 审中-公开

    公开(公告)号：US20190065253A1

    公开(公告)日：2019-02-28

    申请号：US15859370

    申请日：2017-12-30

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Susanne M. Balle ,  Slawomir Putyrski ,  Rahul Khanna ,  Paul Dormitzer

    IPC: G06F9/48 ,  G06N5/02

    Abstract: Technologies for pre-configuring accelerators by predicting bit-streams include communication circuitry and a compute device. The compute device includes a compute engine to determine one or more bit-streams registered on each accelerator of multiple accelerators. The compute engine is further to predict a next job to be requested for acceleration from an application of at least one compute sled of multiple compute sleds, predict a bit-stream from a bit-stream library that is to execute the predicted next job requested to be accelerated, and determine whether the predicted bit-stream is already registered on one of the accelerators. In response to a determination that the predicted bit-stream is not registered on one of the accelerators, the compute engine is to select an accelerator from the plurality of accelerators that satisfies characteristics of the predicted bit-stream and register the predicted bit-stream on the determined accelerator.

    TECHNOLOGIES FOR DYNAMICALLY ALLOCATING DATA STORAGE CAPACITY FOR DIFFERENT DATA STORAGE TYPES
    8.
    发明申请
    TECHNOLOGIES FOR DYNAMICALLY ALLOCATING DATA STORAGE CAPACITY FOR DIFFERENT DATA STORAGE TYPES 审中-公开

    公开(公告)号：US20190034102A1

    公开(公告)日：2019-01-31

    申请号：US15856220

    申请日：2017-12-28

    Applicant: Intel Corporation

    Inventor： Steven MIller ,  Paul Dormitzer

    IPC: G06F3/06

    Abstract: Technologies for allocating data storage capacity on a data storage sled include a plurality of data storage devices communicatively coupled to a plurality of network switches through a plurality of physical network connections and a data storage controller connected to the plurality of data storage devices. The data storage controller is to determine a target storage resource allocation to be used by one or more applications to be executed by one or more sleds in a data center, determine data storage capacity available for each of a plurality of different data storage types on the data storage sled, wherein each data storage type is associated with a different level of data redundancy, determine an amount of data storage capacity for each data storage type to be allocated to satisfy the target storage resource allocation, and adjust the amount of data storage capacity allocated to each data storage type.

    Storage sled for data center
    9.
    发明授权
    Storage sled for data center 有权

    公开(公告)号：US10091904B2

    公开(公告)日：2018-10-02

    申请号：US15394321

    申请日：2016-12-29

    Applicant: INTEL CORPORATION

    Inventor： Steven C. Miller ,  Michael Crocker ,  Aaron Gorius ,  Paul Dormitzer

    IPC: H05K7/14

    Abstract: Examples may include a sled for a rack of a data center including physical storage resources. The sled comprises an array of storage devices and an array of memory. The storage devices and memory are directly coupled to storage resource processing circuits which are themselves, directly coupled to dual-mode optical network interface circuitry. The dual-mode optical network interface circuitry can have a bandwidth equal to or greater than the storage devices.

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